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Digital Logic Design - 2nd Edition - ISBN: 9788185336626, 9781483142227

Digital Logic Design

2nd Edition

Author: B. Holdsworth
eBook ISBN: 9781483142227
Paperback ISBN: 9788185336626
Imprint: Butterworth-Heinemann
Published Date: 1st January 1987
Page Count: 462
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Digital Logic Design, Second Edition provides a basic understanding of digital logic design with emphasis on the two alternative methods of design available to the digital engineer. This book describes the digital design techniques, which have become increasingly important. Organized into 14 chapters, this edition begins with an overview of the essential laws of Boolean algebra, K-map plotting techniques, as well as the simplification of Boolean functions. This text then presents the properties and develops the characteristic equations of a number of various types of flip-flop. Other chapters consider the design of synchronous and asynchronous counters using either discrete flip-flops or shift registers. This book discusses as well the design and implementation of event driven logic circuits using the NAND sequential equation. The final chapter deals with simple coding techniques and the principles of error detection and correction. This book is a valuable resource for undergraduate students, digital engineers, and scientists.

Table of Contents

Preface to the Second Edition

Preface to the First Edition

1 Boolean Algebra

1.1 Introduction

1.2 The Logic of a Switch

1.3 The and Function

1.4 The or Function

1.5 The Inversion Function

1.6 Implementation of Boolean Equations Using Switches or Electronic Gates

1.7 The Idempotency Theorem

1.8 The Theorems of Union and Intersection

1.9 The Redundancy or Absorption Theorem

1.10 The Determination of the Complementary Function

1.11 Theorems on Commutation, Association and Distribution

1.12 The Consensus Theorem


2 Karnaugh Maps and Function Simplification

2.1 Introduction

2.2 Product and Sum Terms

2.3 Canonical Forms

2.4 Boolean Functions of Two Variables

2.5 The Karnaugh Map

2.6 Plotting Boolean Functions On a Karnaugh Map

2.7 Simplification of Boolean Functions

2.8 The Inverse Function

2.9 'Don't-Care' Terms

2.10 The Plotting and Simplification of P-of-S Expressions

2.11 The Quine-McCluskey Tabular Simplification Method

2.12 Properties of Prime Implicant Tables

2.13 Cyclic Prime Implicant Tables

2.14 Semi-Cyclic Prime Implicant Tables

2.15 Simplification of Functions Containing 'Can't Happen' Terms

2.16 The Decimal Approach to Quine-McCluskey


3 NAND and NOR Logic

3.1 Introduction

3.2 The NAND Function

3.3 The Implementation of AND and OR Functions Using NAND Gates

3.4 The Implementation of S-Of-P Expressions Using NAND Gates

3.5 The NOR Function

3.6 The Implementation of OR and AND Functions Using NOR Gates

3.7 The Implementation of P-of-S Expressions Using NOR Gates

3.8 The Implementation of S-of-P Expressions Using NOR Gates

3.9 Gate Expansion

3.10 Miscellaneous Gate

3.11 The Tri-State Gate

3.12 The Exclusive-OR Gate


4 Combinational Logic Design

4.1 Introduction

4.2 The Half-Adder

4.3 The Full Adder

4.4 Full Subtractor

4.5 Comparators

4.6 Parity Generation and Checking

4.7 Code Conversion

4.8 Binary to Gray Code Converter

4.9 Interrupt Sorters


5 Single-Bit Memory Elements

5.1 Introduction

5.2 The T flip-Flop

5.3 The SR Flip-Flop

5.4 The JK Flip-Flop

5.5 The D Flip-Flop

5.6 The Edge-Triggered Flip-Flop

5.7 The Latching Action of a Flip-Flop


6 Counters

6.1 Introduction

6.2 Scale-of-Two Up-Counter

6.3 Scale-of-Four Up-Counter

6.4 Scale-of-Eight Up-Counter

6.5 Scale-of-2N Up-Counter

6.6 Series and Parallel Connection of Counters

6.7 Synchronous Down-Counters

6.8 Scale-of-Five Up-Counter

6.9 Decade Binary Up-Counter

6.10 Decade Binary Down-Counter

6.11 Decade Gray Code 'Up' Counter

6.12 Scale-of-16 Up/Down Counter

6.13 Asynchronous Binary Counters

6.14 Scale-of-Ten Asynchronous Up-Counter

6.15 Asynchronous Resettable Counters

6.16 Integrated-Circuit Counters

6.17 Cascading of IC Counter Chips


7 Shift Register Counters and Generators

7.1 Introduction

7.2 The Four-Bit Shift Register with Parallel Loading

7.3 The Four-Bit Shift-Left, Shift-Right Register

7.4 The Use of Shift Registers as Counters

7.5 The Universal State Diagram for Shift Registers

7.6 The Design of a Decade Counter

7.7 Shift Register Sequence Generators

7.8 The Ring Counter

7.9 The Twisted Ring or Johnson Counter

7.10 Shift Registers with Exclusive-OR Feedback


8 Clock-Driven Sequential Circuits

8.1 Introduction

8.2 Analysis of a Clocked Sequential Circuit

8.3 The Design Procedure for Clocked Sequential Circuits

8.4 The Design of a Sequence Generator

8.5 Moore and Mealy State Machines

8.6 Pulsed Synchronous Circuits

8.7 State Reduction

8.8 State Assignment


9 Event-Driven Circuits

9.1 Introduction

9.2 The Museum Problem

9.3 Races and Cycles

9.4 Race-Free Assignment for a Three-State Machine

9.5 The Pump Problem

9.6 Race-Free Assignment for a Four-State Machine

9.7 A Sequence Detector


10 Digital Design with MSI

10.1 Introduction

10.2 Data Selector or Multiplexer

10.3 The Multiplexer as a Logic Function Generator

10.4 Decoders and Demultiplexers

10.5 Decoder Applications

10.6 Read-Only Memories (ROMs)

10.7 Addressing Techniques for ROMs

10.8 Design of Sequential Circuits Using ROMs

10.9 Programmable Logic Arrays (PLAs)

10.10 Design of Sequential Circuits Using PLAs


11 Arithmetic Circuits

11.1 Introduction

11.2 The Four-Bit Parallel Adder

11.3 The Carry Look-Ahead Adder

11.4 Complement Arithmetic

11.5 The 1'S Complement

11.6 The 2'S Complement

11.7 Representation of Binary Numbers in a Digital Mach

11.8 Addition and Subtraction Using 2'S Complement Arithmetic

11.9 Addition and Subtraction Using L's Complement Arithmetic

11.10 Overflow

11.11 Serial Addition and Subtraction

11.12 Decimal Arithmetic with MSI Adders

11.13 The Use of Complement Arithmetic for Decimal Operations

11.14 Adder/Subtractor for Decimal Arithmetic

11.15 Arithmetic/Logic Unit

11.16 Deisgn of an Arithmetic/Logic Unit

11.17 Combinational Binary Multipliers

11.18 ROM Implemented Binary Multipliers

11.19 The Shift and Add Multiplier

11.20 Binary Division


12 Hazards

12.1 Introduction

12.2 Gate Delays

12.3 The Generation of Spikes

12.4 The Production of Static Hazards in Combinational Networks

12.5 The Elimination of Static Hazards

12.6 Design of Hazard-Free Combinational Networks

12.7 Detection of Hazards in an Existing Network

12.8 Hazard-Free Asynchronous Circuit Design

12.9 Dynamic Hazards

12.10 Essential Hazards


13 Fault Diagnosis in Combinational Circuits

13.1 Introduction

13.2 Fault Detection and Location

13.3 A Fault Test for a 2-Input and Gate

13.4 The Fault Detection Table

13.5 The Fault Location Table

13.6 Adaptive Testing

13.7 Path Sensitisation

13.8 Path Sensitisation Applied to Combinational Networks

13.9 Path Sensitisation in Networks with Fanout

13.10 Two-Level Circuit Fault Detection in AND/OR Circuits

13.11 Two-Level Circuit Fault Detection in OR/AND Circuits

13.12 Tabulation Method of Fault Diagnosis for Two-Level Circuits

13.13 Fault Detection in Multi-Level Circuits

13.14 Boolean Difference

13.15 The Chain Rule


14 Coding Systems for Error Control

14.1 Introduction

14.2 Definition of a Code

14.3 Information Content of the Decimal and Hexadecimal Number Systems

14.4 Coding Theory Terminology

14.5 The Conditions for Error Detection

14.6 The Boolean Circle and the Correction Domain

14.7 The Transmission Equation

14.8 The Undetected Error Rate

14.9 Linear Block Codes

14.10 Backward Error Correction

14.11 Matrix Representation of Linear Block Codes

14.12 Decoding the Received Word

14.13 Forward Error Correction


Answers to Problems




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© Butterworth-Heinemann 2014
1st January 1987
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About the Author

B. Holdsworth

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