For those with a basic understanding of digital design, this book teaches the essential skills to design digital integrated circuits using Verilog and the relevant extensions of SystemVerilog. In addition to covering the syntax of Verilog and SystemVerilog, the author provides an appreciation of design challenges and solutions for producing working circuits. The book covers not only the syntax and limitations of HDL coding, but deals extensively with design problems such as partitioning and synchronization, helping you to produce designs that are not only logically correct, but will actually work when turned into physical circuits. Throughout the book, many small examples are used to validate concepts and demonstrate how to apply design skills.

This book takes readers who have already learned the fundamentals of digital design to the point where they can produce working circuits using modern design methodologies. It clearly explains what is useful for circuit design and what parts of the languages are only software, providing a non-theoretical, practical guide to robust, reliable and optimized hardware design and development.

Key Features

  • Produce working hardware: Covers not only syntax, but also provides design know-how, addressing problems such as synchronization and partitioning to produce working solutions
  • Usable examples: Numerous small examples throughout the book demonstrate concepts in an easy-to-grasp manner
  • Essential knowledge: Covers the vital design topics of synchronization, essential for producing working silicon; asynchronous interfacing techniques; and design techniques for circuit optimization, including partitioning


Professional engineers; potential for use as background reading on graduate and senior undergraduate courses

Table of Contents

  • About the author
  • Preface
  • Acknowledgments
  • Chapter 1: Introduction
    • Abstract
    • Who should read this book
    • Hardware description languages and methodology
    • What this book covers
    • Historical perspective
    • Verilog and Systemverilog
    • Book organization
  • Chapter 2: Bottom-up design
    • Abstract
    • Primitive instantiation
    • Designing with primitives
    • Identifiers and escaped identifiers
    • Bus declarations
    • Design hierarchy and test fixtures
    • Port association
    • Timescales
    • Summary
  • Chapter 3: Behavioral coding part I: blocks, variables, and operators
    • Abstract
    • Top-down design
    • Synthesizable and nonsynthesizable code
    • Register Transfer Level (RTL)
    • Continuous assignments
    • Implicit continuous assignments
    • Functional blocks: always and initial
    • Named blocks
    • Sensitivity lists
    • Splitting assignments
    • Variables
    • Operators
    • Summary
  • Chapter 4: Behavioral coding part II: defines, parameters, enumerated types, and packages
    • Abstract
    • Global definitions
    • Parameters
    • Overriding default values
    • Local parameters
    • Specify parameters
    • Enumerated types
    • Constants
    • Packages
    • Filling a scalable variable with all ones
    • Summary
  • Chapter 5: Behavioral coding part III: loops and branches
    • Abstract
    • Loops
    • Case statements
    • Latch generation
    • Unique and priority
    • Summary
  • Chapter 6: Subroutines and interfaces
    • Abstract
    • Subroutines
    • Tasks
    • Functions
    • Parameters in su


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© 2015
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About the author