Digital Design and Computer Architecture

Digital Design and Computer Architecture

1st Edition - March 2, 2007

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  • Authors: David Harris, Sarah Harris
  • eBook ISBN: 9780080547060

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Description

Digital Design and Computer Architecture is designed for courses that combine digital logic design with computer organization/architecture or that teach these subjects as a two-course sequence. Digital Design and Computer Architecture begins with a modern approach by rigorously covering the fundamentals of digital logic design and then introducing Hardware Description Languages (HDLs). Featuring examples of the two most widely-used HDLs, VHDL and Verilog, the first half of the text prepares the reader for what follows in the second: the design of a MIPS Processor. By the end of Digital Design and Computer Architecture, readers will be able to build their own microprocessor and will have a top-to-bottom understanding of how it works--even if they have no formal background in design or architecture beyond an introductory class. David Harris and Sarah Harris combine an engaging and humorous writing style with an updated and hands-on approach to digital design.

Key Features

  • Unique presentation of digital logic design from the perspective of computer architecture using a real instruction set, MIPS.
  • Side-by-side examples of the two most prominent Hardware Design Languages--VHDL and Verilog--illustrate and compare the ways the each can be used in the design of digital systems.
  • Worked examples conclude each section to enhance the reader's understanding and retention of the material.

Readership

students taking a course that combines digital logic and computer architecture or students taking a two-quarter sequence in digital logic and computer organization/architecture

Table of Contents

  • Table of Contents

    1 From Zero to One
    1.1 The Game Plan
    1.2 The Art of Managing Complexity
    1.3 The Digital Abstraction
    1.4 Number Systems
    1.5 Logic Gates
    1.6 Logic Levels
    1.7 * CMOS Transistors
    1.8 * Power Consumption
    1.9 Summary and A Look Ahead

    2 Combinational Logic Design
    2.1 Introduction
    2.2 Boolean Equations
    2.3 Boolean Algebra
    2.4 From Logic to Gates
    2.5 Multilevel Combinational Logic
    2.6 X's and Z's, Oh My
    2.7 Karnaugh Maps
    2.8 Combinational Building Blocks
    2.9 Timing
    2.10 Summary

    3 Sequential Logic Design
    3.1 Introduction
    3.2 Latches and Flip-Flops
    3.3 Synchronous Logic Design
    3.4 Finite State Machines
    3.5 Timing of Sequential Logic
    3.6 Parallelism
    3.7 Summary

    4 Hardware Description Languages
    4.1 Introduction
    4.2 Combinational Logic
    4.3 Structural Modeling
    4.4 Sequential Logic
    4.5 More Combinational Logic
    4.6 Finite State Machines
    4.7 * Parameterized Modules
    4.8 Testbenches
    4.9 Summary

    5 Digital Building Blocks
    5.1 Introduction
    5.2 Arithmetic Circuits
    5.3 Number Systems
    5.4 Sequential Building Blocks
    5.5 Memory Arrays
    5.6 Logic Arrays
    5.7 Summary

    6 Architecture
    6.1 Introduction
    6.2 Assembly Language
    6.3 Machine Language
    6.4 Programming
    6.5 Addressing Modes
    6.6 Lights, Camera, Action: Compiling, Assembling, and Loading
    6.7 * Odds and Ends
    6.8 * Real World Perspective: IA-32 Architecture
    6.9 Summary

    7 Microarchitecture
    7.1 Introduction
    7.2 Performance Analysis
    7.3 Single-Cycle Processor
    7.4 Multicycle Processor
    7.5 Pipelined Processor
    7.6 * HDL Representation
    7.7 * Exceptions
    7.8 * Advanced Microarchitecture
    7.9 * Real World Perspective: IA-32 Microarchitecture
    7.10 Summary

    8 Memory Systems
    8.1 Introduction
    8.2 Memory System Performance Analysis
    8.3 Caches
    8.4 Virtual Memory
    8.5 * Memory-Mapped I/O
    8.6 * Real World Perspective: IA-32 Memory and I/O Systems
    8.7 Summary

    Appendix A Digital System Implementation
    A.1 Introduction
    A.2 74xx Logic
    A.3 Programmable Logic
    A.4 Application-Specific Integrated Circuits
    A.5 Data Sheets
    A.6 Logic Families
    A.7 Packaging and Assembly
    A.8 Transmission lines
    A.9 Economics

    Appendix B MIPS Instructions

Product details

  • No. of pages: 592
  • Language: English
  • Copyright: © Morgan Kaufmann 2007
  • Published: March 2, 2007
  • Imprint: Morgan Kaufmann
  • eBook ISBN: 9780080547060

About the Authors

David Harris

David Harris
David Harris is the Harvey S. Mudd Professor of Engineering Design at Harvey Mudd College. He received his Ph.D. in electrical engineering from Stanford University and his M.Eng. in electrical engineering and computer science from MIT. Before attending Stanford, he worked at Intel as a logic and circuit designer on the Itanium and Pentium II processors. Since then, he has consulted at Sun Microsystems, Hewlett-Packard, Broadcom, and other design companies. David holds more than a dozen patents and is the author of three other textbooks on chip design, as well as many Southern California hiking guidebooks. When he is not working, he enjoys hiking, flying, and making things with his three sons.

Affiliations and Expertise

Associate Professor of Engineering, Harvey Mudd College, Claremont, CA, USA

Sarah Harris

Sarah Harris
Sarah L. Harris is an Assistant Professor of Engineering at Harvey Mudd College. She received her Ph.D. and M.S. in Electrical Engineering from Stanford University. Before attending Stanford, she received a B.S. in Electrical and Computer Engineering from Brigham Young University. Sarah has also worked with Hewlett-Packard, the San Diego Supercomputer Center, Nvidia, and Microsoft Research in Beijing.

Sarah loves teaching, exploring and developing new technologies, traveling, wind surfing, rock climbing, and playing the guitar. Her recent exploits include researching sketching interfaces for digital circuit design, acting as a science correspondent for a National Public Radio affiliate, and learning how to kite surf. She speaks four languages and looks forward to learning more in the near future.

Affiliations and Expertise

Assistant Professor of Engineering, Harvey Mudd College, Claremont, CA, USA

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