Customizable Embedded Processors
Design Technologies and Applications
Resources
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Customizable processors have been described as the next natural step in the evolution of the microprocessor business: a step in the life of a new technology where top performance alone is no longer sufficient to guarantee market success. Other factors become fundamental, such as time to market, convenience, energy efficiency, and ease of customization. This book is the first to explore comprehensively one of the most fundamental trends which emerged in the last decade: to treat processors not as rigid, fixed entities, which designers include “as is” in their products; but rather, to build sound methodologies to tailor-fit processors to the specific needs of such products. This book addresses the goal of maintaining a very large family of processors, with a wide range of features, at a cost comparable to that of maintaining a single processor.
Key Features
- First book to present comprehensively the major ASIP design methodologies and tools without any particular bias
- Written by most of the pioneers and top international experts of this young domain
- Unique mix of management perspective, technical detail, research outlook, and practical implementation
Readership
Engineers in industry working in embedded software, system architectures, processor architectures and design tools. Academic researchers
Table of Contents
- Introduction
Business Opportunities: The Case of Wireless Applications
Logistic Challenges: Lofty Ambitions and Stark Realities of Customizing Processors
Architectural Description Languages
Retargetable Toolsets
Processor Configuration
Automatic Instruction-Set Extensions
Challenges to Automatic Customization
Toolset Support for Instruction-Set Extensions
Coprocessor Generation from Executable Code
Datapath Synthesis
Instruction Matching and Modelling
Processor Verification
Sub-RISC Processors
An ASIP for UMTS-FDD Cell Search
Hardware/software Trade-offs for Advanced 3G Channel Decoding
FPGA-Based Processor Implementation
Designing a H.264 Encoder with Real-World Tradeoffs
Product details
- No. of pages: 528
- Language: English
- Copyright: © Morgan Kaufmann 2006
- Published: July 14, 2006
- Imprint: Morgan Kaufmann
- Hardcover ISBN: 9780123695260
- eBook ISBN: 9780080490984
About the Authors
Paolo Ienne
Affiliations and Expertise
Professor, Processor Architecture Laboratory, Swiss Federal Institute of Technology of Lausanne, Switzerland
Rainer Leupers
Affiliations and Expertise
Professor of Software Systems on Silicon, RWTH Aachen University, Germany.