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The topic areas presented within this volume focus on design environments and the applications of hardware description and modelling – including simulation, verification by correctness proofs, synthesis and test. The strong relationship between the topics of CHDL'91 and the work around the use and re-standardization of the VHDL language is also explored. The quality of this proceedings, and its significance to the academic and professional worlds is assured by the excellent technical programme here compiled.
Keynote: Some Issues in HDL-based Behaviour Modelling (R. Piloty, - Germany). Sessions: Verification 1 (C.D. Kloos, - Spain, Chair.): From a HDL Description to Formal Proof Systems: Principles and Mechanization (L. Pierre - France), Specification and Verification of Hardware Systems Using the Temporal Logic Language TRIO (A. Coen-Porisini, A. Morzenti, D. Sciuto, - Italy), A Methodology for Proving Correctness of Parameterized Hardware Modules in HOL (C.M. Angelo, L. Claesen, H. De Man, - Belgium). Simulation 1 (P. Bakowski, - France, Chair.): An Exercise in VHDL Timing Back-Annotation (G. Jennings - Sweden), Behavioral Level Modeling of Gate Level Loading Effects (Z. Navabi - USA), Putting Different Simulation Models Together - The Simulation Configuration Language VHDL/S (A. Oczko, C. Oczko - Germany). Verification 2 (E. Clarke - USA, Chair.): Abstraction Mechanisms for Hardware Verification: Formalisation in a Process Algebra (A. Bailey - UK), Verification of Synchronous Sequential Circuits Obtained from Algorithmic Specifications (F. Corella, R. Camposano, R. Bergamaschi, M. Payer - USA), A Method for Symbolic Verification of Synchronous Circuits (T. Filkorn - Germany). Design Environments 1 (F. Wagner - Brazil, Chair.): Operation/Event Graphs: A Design Representation for Timing Behavior (T. Amon, G. Borriello, C. Séquin - USA), A New Timed Petri Net Model for Hardware Representation (G. Buonanno, S. Morasca, M. Pezzè, K. Portman, D. Sciuto - Italy), An Object-Oriented Framework Supporting the Full High-Level Synthesis Trajectory (D. Lanneer, et al.- Belgium). Synthesis (R. Camposano - USA, Chair.):VHDL Extensions Needed for Synthesis and Design (D. Agnew - Canada), Hierarchical Action Refinement: A Methodology for Compiling Asynchronous Circuits from a Concurrent HDL (V. Akella, G. Gopalakrishnan - USA), EDISYN: A Language-Based Editor for High-Level Synthesis (C. Chang, G.M. Brown, M.E. Leeser - USA). Design Environment 2 (F. Rammig - Germany, Chair.): A Constraint-Driven Approach to Configuration Binding in an Object-Oriented VHDL CAD System (N.D. Dutt, J.H. Cho, T. Hadley - USA). Test (D. Agnew - Canada, Chair.): VHDL Semantics for Behavioral Test Generation (C.H. Cho, J.R. Armstrong - USA), Using a VHDL Description to Generate Hardware Test (P. Wodey, C. Robach - France), Functional Tests for Hardware Derived from VHDL Description (H. Hümmer, H. Veit, H. Töpfer - Germany). Invited Papers: Declarative Languages - Still a Long Way to Go (R. Boute - The Netherlands), Experience in Designing Formally Verifiable HDL's (H. Eveking - Germany). Short Papers: (M.J. Chung - USA, Chair.): High Level Specification and Synthesis of Sequential Logic Modules (P. Hou, R.M. Owens, M.J. Irwin - USA), Fully Generic Description of Hardware in VHDL (J.J. Joyce, J.P. Van Tassel - Canada), Integrating Hardware Verification with CHDLs (S. Rajgopal, K. Hedlund, D. Reeves - USA), SpecCharts: A Language for System Level Synthesis (F. Vahid, S. Narayan, D.D. Gasjki - USA), Description Methods of CHDL for Redesign Methods (M. Fujita - Japan).
- No. of pages:
- © North Holland 1991
- 17th October 1991
- North Holland
- eBook ISBN:
IMAG-ARTEMIS Laboratory, Grenoble, France
University of Virginia, Charlottesville, VA, USA