Volume 32. Computer Hardware Description Languages and their Applications

1st Edition

Proceedings of the 11th IFIP WG10.2 International Conference on Computer Hardware Description Languages and their Applications - CHDL '93 Sponsored by IFIP WG10.2 and in cooperation with IEEE COMPSOC, Ottawa, Ontario, Canada, 26-28 April, 1993



Hardware description languages (HDLs) have established themselves as one of the principal means of designing electronic systems. The interest in and usage of HDLs continues to spread rapidly, driven by the increasing complexity of systems, the growth of HDL-driven synthesis, the research on formal design methods and many other related advances.

This research-oriented publication aims to make a strong contribution to further developments in the field. The following topics are explored in depth: BDD-based system design and analysis; system level formal verification; formal reasoning on hardware; languages for protocol specification; VHDL; HDL-based design methods; high level synthesis; and text/graphical HDLs. There are short papers covering advanced design capture and recent work in high level synthesis and formal verification. In addition, several invited presentations on key issues discuss and summarize recent advances in real time system design, automatic verification of sequential circuits and languages for protocol specification.

Table of Contents

Preface. Conference Organization. Invited Presentation: Real time distributed systems (M.R. Barbacci). BDD-based Design and Analysis Techniques. (Chair: L. Claesen). Verification of the Futurebus+ Cache coherence protocol (E.M. Clarke, O. Grumberg, H. Hiraishi, S. Jha, D.E. Long, K.L. McMillan, L.A. Ness). Exploiting symbolic traversal techniques for efficient Process Algebra Manipulation (P. Camurati, F. Corno, P. Prinetto). Hardware-verification using first order BDDs (K. Schneider, R. Kumar, T. Kropf). HDL-based Design Methods. (Chair: F. Rammig). HW/SW co-design with PRAMs using codes (K. Buchenrieder, A. Sedlmeier, C. Veith). Prevail-DM: a framework-based environment for formal hardware verification (F.R. Wagner). Better verification through symmetry (C.N. Ip, D.L. Dill). Synthesis and Verification. (Chair: M. Barbacci). A rewriting based method for the formal verification of microprocessors (M. Allemand). Reasoning about the VHDL standard logic package signal data type (J.W. Gambles, P.J. Windley). An efficient data-path synthesis based on algorithmic description under the constraints of time and area (X.-J. Xu, M. Ishizuka). Integrating Boolean verification with formal derivation (B. Bose, S.D. Johnson, S. Pullela). Automated high-level verification against clocked algorithmic specifications (F. Corella). The backward walk approach in FSM verification (S. Krischer). Invited Presentation: Automatic verification of sequential circuit designs (E.M. Clarke). Protocol Specification. (Chair: E. Cerny). Toward a basis for protocol specification and process decomposition (K. Rath, S.D. Johnson). Integrating SDL and VHDL for system-level hardware design (W. Glunz, T. Kruse, T. Rössel, D. Monjau). Formal Reasoning about Regular Structures. (Chair: C.D. Kloos). Reasoning about array structures using a dependently typed logic (A. Dent, K. Hanna


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© 1993
North Holland
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About the editors

D. Agnew

Affiliations and Expertise

Bell-Northern Research, Ottawa, Ontario, Canada

L. Claesen

Affiliations and Expertise

Interuniversity Micro-Electronics Center & Katholieke Universiteit Leuven, Belgium

R. Camposano

Affiliations and Expertise

German National Research Center for Computer Science, GMD/SET, Sankt Augustin, Germany