One of the biggest challenges in chip and system design is determining whether the hardware works correctly. That is the job of functional verification engineers and they are the audience for this comprehensive text from three top industry professionals. As designs increase in complexity, so has the value of verification engineers within the hardware design team. In fact, the need for skilled verification engineers has grown dramatically--functional verification now consumes between 40 and 70% of a project's labor, and about half its cost. Currently there are very few books on verification for engineers, and none that cover the subject as comprehensively as this text. A key strength of this book is that it describes the entire verification cycle and details each stage. The organization of the book follows the cycle, demonstrating how functional verification engages all aspects of the overall design effort and how individual cycle stages relate to the larger design process. Throughout the text, the authors leverage their 35 plus years experience in functional verification, providing examples and case studies, and focusing on the skills, methods, and tools needed to complete each verification task. Additionally, the major vendors (Mentor Graphics, Cadence Design Systems, Verisity, and Synopsys) have implemented key examples from the text and made these available on line, so that the reader can test out the methods described in the text.

Key Features

* Comprehensive overview of the complete verification cycle * Combines industry experience with a strong emphasis on functional verification fundamentals * Includes real-world case studies and downloadable software implementations of key examples from the major vendors (Mentor Graphics, Cadence Design Systems, Verisity, and Synopsys)


Sr. undergraduate & graduate students in functional verification courses in EE and Computer Engineering Departments; new and experienced verification engineers

Table of Contents

Comprehensive Functional Verification: The Complete Industry Cycle Part I: Introduction to Verification Chapter 1: Verification in the Chip Design Process 1.1 Introduction to Functional Verification 1.2 The Verification Challenge 1.3 Mission and Goals of Verification 1.4 Cost of Verification 1.5 Areas of Verification beyond the scope of this book 1.6 The Verification Cycle: A Structured Process 1.7 Summary 1.8 Exercises Chapter 2: Verification Flow 2.1 Verification Hierarchy 2.2 Strategy of Verification 2.3 Summary 2.4 Exercises Chapter 3: Fundamentals of Simulation Based Verification 3.1 Basic Verification Environment: A Test Bench 3.2 Observation Points: Black-box, White-box and Grey-box verification 3.3 Assertion Based Verification – An overview 3.4 Test benches and Testing Strategies 3.5 Summary 3.6 Exercises Chapter 4: The Verification Plan 4.1 The Functional Specification 4.2 The Evolution of the Verification Plan 4.3 Contents of the Verification Plan 4.4 Verification example: Calc1 4.5 Summary 4.6 Exercises Part II: Simulation Based Verification Chapter 5: HDLs and Simulation Engines 5.1 Hardware Description Languages 5.2 Simulation Engines - Introduction 5.3 Event-Driven Simulation 5.4 Improving Simulation Throughput 5.5 Cycle-Based Simulation 5.6 Waveform Viewers 5.7 Summary 5.8 Exercises Chapter 6: Creating Environments 6


No. of pages:
© 2005
Morgan Kaufmann
eBook ISBN:
Print ISBN:

About the authors

Bruce Wile

Affiliations and Expertise

IBM Corporation, Poughkeepsie, NY

John Goss

Affiliations and Expertise

IBM Corporation, Research Triangle Park, NC

Wolfgang Roesner

Affiliations and Expertise

IBM Corporation, Austin, TX


Very good :-)