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ASIC and FPGA Verification

A Guide to Component Modeling

  • 1st Edition - September 29, 2004
  • Author: Richard Munden
  • Language: English
  • eBook ISBN:
    9 7 8 - 0 - 0 8 - 0 4 7 5 9 2 - 9

Richard Munden demonstrates how to create and use simulation models for verifying ASIC and FPGA designs and board-level designs that use off-the-shelf digital components. Based on… Read more

ASIC and FPGA Verification

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Richard Munden demonstrates how to create and use simulation models for verifying ASIC and FPGA designs and board-level designs that use off-the-shelf digital components. Based on the VHDL/VITAL standard, these models include timing constraints and propagation delays that are required for accurate verification of today’s digital designs. ASIC and FPGA Verification: A Guide to Component Modeling expertly illustrates how ASICs and FPGAs can be verified in the larger context of a board or a system. It is a valuable resource for any designer who simulates multi-chip digital designs.