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By
Richard Yanda, Semiconductor Services, Redwood City, CA, USA
Michael Heynes, Semiconductor Services, Redwood City, CA, USA
Anne Miller, Semiconductor Services, Redwood City, CA, USA
Description
This book takes the reader through the actual manufacturing process of making a typical chip, from start to finish, including a detailed
discussion of each step, in plain language. The evolution of today's technology is added to the story, as seen through the eyes of the
engineers who solved some of the problems. The authors are well suited to that discussion since they are three of those same engineers.
They have a broad exposure to the industry and its technology that extends all the way back to Shockley Laboratories, the first semiconductor
manufacturer in Silicon Valley.
The CMOS (Complementary Metal-Oxide-Semiconductor) process flow is the focus of the discussion and is
covered in ten chapters. The vast majority of chips made today are fabricated using this general method. In order to ensure that all
readers are comfortable with the vocabulary, the first chapter carefully and clearly introduces the science concepts found in later chapters.
A chapter is devoted to pointing out the differences in other manufacturing methods, such as the gallium arsenide technology that produces
chips for cell phones. In addition, a chapter describing the nature of the semiconductor industry from a business perspective is included.
"The entire process of making a chip is surprisingly easy to understand. The part of the story that defies belief is the tiny dimensions:
the conducting wires and other structures on a chip are more than a hundred times thinner than a hair - and getting thinner with every
new chip design."
Audience
Electronics engineers, engineering managers, and students
Contents
Foreward
Acknowledgements
About the Authors
What?s on the CD-ROM?
1. IC Fabrication Overview
a. Introduction
b. Support Technologies
c. Integrated Circuit Fabrication
d. Test and Assembly
e. Summary
2. Support Technologies
a. Introduction
b. Contamination Control
c.
Crystal Growth and Wafer Preparation
d. Circuit Design
e. Photomask and Reticle Preparation
3. Forming Wells
a. Introduction
b. Initial
Oxidation
c. Photolithography
d. Ion Implantation
4. Isolate Active Areas (Shallow Trench Isolation)
a. Introduction to Shallow Trench
Isolation
b. Pad Oxide Growth
c. Silicon Nitride Deposition
d. Photolithography for Photo/Etch
e. Hard Mask Formation Using Plasma Etch
f. Form Trenches in Silicon with Plasma Etch
g. Fill Trenches with Silicon Dioxide
h. Chemical Mechanical Polishing (CMP) to Remove Excess
Dioxide
i. Wet Etch Removal of Silicon Nitride and Pad Oxide
5. Building the Transistors
a. Introduction
b. Thin Film Formation
c. Poly
Gate Formation
d. Source/Drain Formation
e. Salicide Formation
6. First Level Metallization
a. Introduction
b. Nitride and Oxide Depositions
c. CMP Planarization
d. Photo/Etch for Contact Holes
e. Tungsten Plug Process
f. Low-k Dielectric Process
g. Copper First Level Interconnection
Process
7. Multilevel Metal Interconnects and Dual Damascene
a. Introduction
b. Deposit Barrier Layer and Intermetal Dielectric
c. Dual
Damascene Process
d. Form Bonding Pads
e. Final Passivation Process
8. Test and Assembly
a. Introduction
b. Wafer and Chip Testing
c.
Assembly and Packaging
Appendix A: Science Overview
Introduction
1. Atoms and Molecules
2. Gases
3. Chemistry
4. Solids
5. Electricity,
Electric and Magnetic Fields
Appendix B: Plasma Etch Supplement to Chapter 4
1. Plasma Etcher Theory
2. Plasma Etch Process Requirements
Bibliography
Index
| Bibliographic details |
Paperback, 280 pages, publication date: APR-2005
ISBN-13: 978-0-7506-7760-8
ISBN-10: 0-7506-7760-0
Imprint: NEWNES
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Last update: 5 Sep 2009
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