Three-dimensional Integrated Circuit Design book cover

Three-dimensional Integrated Circuit Design

With vastly increased complexity and functionality in the "nanometer era" (i.e. hundreds of millions of transistors on one chip), increasing the performance of integrated circuits has become a challenging task. Connecting effectively (interconnect design) all of these chip elements has become the greatest determining factor in overall performance. 3-D integrated circuit design may offer the best solutions in the near future. This is the first book on 3-D integrated circuit design, covering all of the technological and design aspects of this emerging design paradigm, while proposing effective solutions to specific challenging problems concerning the design of 3-D integrated circuits. A handy, comprehensive reference or a practical design guide, this book provides a sound foundation for the design of 3-D integrated circuits.

Audience
VLSI design engineers, CAD Designers of Microprocessors and Systems-on-Chip (SOC), concerned with 3-D integration in chip design...INTERCONNECT, at companies globally such as Microsoft, Honeywell, Intel, AMD, IBM, HP, NVIDIA, Marvell, Texas Instruments, Samsung, Hitachi, Sony, Fujitsu, Toshiba, ST Microelectronics, NXP, Freescale, Infineon, NOKIA, Qualcom, Cadence, Synopsys, Magma, Mentor Graphics, Tezzaron Inc, Ziptronix,Tru-Si, IMEC Belgium, etc.

Paperback, 336 Pages

Published: September 2008

Imprint: Morgan Kaufmann

ISBN: 978-0-12-374343-5

Contents

  • Chapter 1. Introduction Chapter 2. Manufacturing of 3-D Packaged SystemsChapter 3. 3-D Integrated Circuit Fabrication Technologies Chapter 4. Interconnect Prediction Models Chapter 5. Physical Design Techniques for 3-D ICsChapter 6. Thermal Management Techniques Chapter 7. Timing Optimization for Two-Terminal Interconnects Chapter 8. Timing Optimization for Multi-Terminal Interconnects Appendix A: Enumeration of Gate Pairs in a 3-D IC Appendix B: Formal Proof of Optimum Single Via Placement Appendix C: Proof of the Two-Terminal Via Placement HeuristicAppendix D: Proof of Condition for Via Placement of Multi-Terminal Nets References

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