The Designer's Guide to VHDLBy
- Peter Ashenden, Adjunct Associate Professor, School of Computer Science, University of Adelaide, Australia
Since the publication of the first edition of The Designer's Guide to VHDL in 1996, digital electronic systems have increased exponentially in their complexity, product lifetimes have dramatically shrunk, and reliability requirements have shot through the roof. As a result more and more designers have turned to VHDL to help them dramatically improve productivity as well as the quality of their designs.
VHDL, the IEEE standard hardware description language for describing digital electronic systems, allows engineers to describe the structure and specify the function of a digital system as well as simulate and test it before manufacturing. In addition, designers use VHDL to synthesize a more detailed structure of the design, freeing them to concentrate on more strategic design decisions and reduce time to market. Adopted by designers around the world, the VHDL family of standards have recently been revised to address a range of issues, including portability across synthesis tools.
This best-selling comprehensive tutorial for the language and authoritative reference on its use in hardware design at all levels--from system to gates--has been revised to reflect the new IEEE standard, VHDL-2001. Peter Ashenden, a member of the IEEE VHDL standards committee, presents the entire description language and builds a modeling methodology based on successful software engineering techniques. Reviewers on Amazon.com have consistently rated the first edition with five stars. This second edition updates the first, retaining the authors unique ability to teach this complex subject to a broad audience of students and practicing professionals.
Published: May 2001
Imprint: Morgan Kaufmann
"The second edition of The Designer's Guide to VHDL sets a new standard in VHDL texts. I am certain that you will find it a very valuable addition to your library."
From the foreword by Paul Menchini, Menchini & Associates
- 1 Fundamental Concepts1.1 Modeling Digital Systems1.2 Domains and Levels of Modeling1.3 Modeling Languages1.4 VHDL Modeling Concepts1.5 Learning a New Language: Lexical Elements and SyntaxExercises2 Scalar Data Types and Operations2.1 Constants and Variables2.2 Scalar Types2.3 Type Classification2.4 Attributes of Scalar Types2.5 Expressions and OperatorsExercises3 Sequential Statements3.1 If Statements3.2 Case Statements3.3 Null Statements3.4 Loop Statements3.5 Assertion and Report StatementsExercises4 Composite Data Types and Operations4.1 Arrays4.2 Unconstrained Array Types4.3 Array Operations and Referencing4.4 RecordsExercises5 Basic Modeling Constructs5.1 Entity Declarations5.2 Architecture Bodies5.3 Behavioral Descriptions5.4 Structural Descriptions5.5 Design ProcessingExercises6 Case Study: A Pipelined Multiplier Accumulator6.1 Algorithm Outline6.2 A Behavioral Model6.3 A Register-Transfer-Level ModelExercises7 Subprograms7.1 Procedures7.2 Procedure Parameters7.3 Concurrent Procedure Call Statements7.4 Functions7.5 Overloading7.6 Visibility of DeclarationsExercises8 Packages and Use Clauses8.1 Package Declarations8.2 Package Bodies8.3 Use Clauses8.4 The Predefined Package Standard8.5 IEEE Standard PackagesExercises9 Aliases9.1 Aliases for Data Objects9.2 Aliases for Non-Data ItemsExercises10 Case Study: A Bit-Vector Arithmetic Package10.1 The Package Interface10.2 The Package Body10.3 An ALU Using the Arithmetic PackageExercises11 Resolved Signals11.1 Basic Resolved Signals11.2 IEEE Std_Logic_1164 Resolved Subtypes11.3 Resolved Signals and Ports11.4 Resolved Signal ParametersExercises12 Generic Constants12.1 Parameterizing Behavior12.2 Parameterizing StructureExercises13 Components and Configurations13.1 Components13.2 Configuring Component Instances13.3 Configuration SpecificationsExercises14 Generate Statements14.1 Generating Iterative Structures14.2 Conditionally Generating Structures14.3 Configuration of Generate StatementsExercises15 Case Study: The DLX Computer System15.1 Overview of the DLX CP15.2 A Behavioral Model15.3 Testing the Behavioral Model15.4 A Register-Transfer-Level Model15.5 Testing the Register-Transfer-Level ModelExercises16 Guards and Blocks16.1 Guarded Signals and Disconnection16.2 Blocks and Guarded Signal Assignment16.3 Using Blocks for Structural ModularityExercises17 Access Types and Abstract Data Types17.1 Access Types17.2 Linked Data Structures17.3 Abstract Data Types Using PackagesExercises18 Files and Input/Output18.1 Files18.2 The Package TextioExercises19 Case Study: Queuing Networks19.1 Queuing Network Concepts19.2 Queuing Network Modules19.3 A Queuing Network for a Disk SystemExercises20 Attributes and Groups20.1 Predefined Attributes20.2 User-Defined AttributesExercises21 Miscellaneous Topics21.1 Buffer and Linkage Ports21.2 Conversion Functions in Association Lists21.3 Postponed Processes21.4 Shared VariablesExercisesA SynthesisA.1 Use of Data TypesA.2 Interpretation of Standard Logic ValuesA.3 Modeling Combinatorial LogicA.4 Modeling Sequential LogicA.5 VHDL Modeling RestrictionsB The Predefined Package StandardC IEEE Standard PackagesC.1 Std_Logic_1164 Multiv-Value Logic SystemC.2 Standard 1076.3 VHDL Synthesis PackagesC.3 Standard 1076.2 VHDL Mathematical PackagesD Related StandardsD.1 IEEE VHDL StandardsD.2 Other Design Automation StandardsE VHDL SyntaxE.1 Design FileE.2 Library Unit DeclarationsE.3 Declarations and SpecificationsE.4 Type DefinitionsE.5 Concurrent StatementsE.6 Sequential StatementsE.7 Interfaces and AssociationsE.8 ExpressionsF DifferencesG Answers to ExercisesReferencesIndex