The Designer's Guide to VHDL


  • Peter Ashenden, Adjunct Associate Professor, School of Computer Science, University of Adelaide, Australia

VHDL, the IEEE standard hardware description language for describing digital electronic systems, has recently been revised. This book has become a standard in the industry for learning the features of VHDL and using it to verify hardware designs. This third edition is the first comprehensive book on the market to address the new features of VHDL-2008.
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Hardware Verification Engineers using VHDL


Book information

  • Published: May 2008
  • ISBN: 978-0-12-088785-9

Table of Contents

1 Fundamental Concepts2 Scalar Data Types and Operations3 Sequential Statements4 Composite Data Types and Operations5 Basic Modeling Constructs6 Case Study: A Pipelined Complex Multiplier Accumulator7 Subprograms8 Packages and Use Clauses9 Aliases10 External Names in Testbenches11 Properties and Assertion-Based Design12 Resolved Signals13 Generics14 Components and Configurations15 Generate Statements16 Access Types and Abstract Data Types17 Files and Input/Output18 Case Study: Queuing Networks19 Attributes and Groups20 Design for Synthesis21 Case Study: System Design using the Gumnut Core22 Miscellaneous TopicsA Standard PackagesB Related StandardsC VHDL SyntaxD Differences Among VHDL VersionsE Answers to ExercisesReferencesIndex