The Art of Multiprocessor Programming
By- Maurice Herlihy, Professor of Computer Science, Brown University, Providence, RI, USA
- Maurice Herlihy, Professor of Computer Science, Brown University, Providence, RI, USA
- Nir Shavit, Professor of Computer Science, Tel Aviv University, Israel
- Nir Shavit, Professor of Computer Science, Tel Aviv University, Israel
As the computer industry changes from single-processor to multiprocessor architectures, this revolution requires a fundamental change in how programs are written. To leverage the performance and power of multiprocessor programming, also known as multicore programming, you need to learn the new principles, algorithms, and tools presented in this book. It includes fully-developed Java examples detailing data structures, synchronization techniques, transactional memory, and more.
Prof. Maurice Herlihy, who coined the phrase "transactional memory," is on the faculty of Brown University. He is the recipient of the 2003 Dijkstra Prize in distributed computing. Prof. Nir Shavit is on the faculty of Tel-Aviv University and a member of the technical staff at Sun Microsystems Laboratories. In 2004 they shared the GUdel Prize, the highest award in theoretical computer science.
Audience
Students in multiprocessor and multicore programming courses and engineers working with multiprocessor and multicore systems.
Paperback, 528 Pages
Published: February 2008
Imprint: Morgan Kaufmann
ISBN: 978-0-12-370591-4
Contents
- 1 Introduction; 2 Mutual Exclusion; 3 Concurrent Objects and Linearization; 4 Foundations of Shared Memory; 5 The Relative Power of Synchronization Methods; 6 The Universality of Consensus; 7 Spin Locks and Contention; 8 Monitors and Blocking Sychronization; 9 Linked Lists: the Role of Locking; 10 Concurrent Queues and the ABA Problem; 11 Concurrent Stakcs and Elimination; 12 Counting, Sorting and Distributed Coordinatino; 13 Concurrent Hashing and Natural Parallelism; 14 Skiplists and Balanced Search; 15 Priority Queues; 16 Futures, Scheduling and Work Distribution; 17 Barriers; 18 Transactional Memory; Appendices
