Synchronous Precharge Logic


  • Marek Smoszna, Memory design engineer, NVIDIA Corporation, Sunnyvale, CA, USA

Precharge logic is used by a variety of industries in applications where processor speed is the primary goal, such as VLSI (very large systems integration) applications. Also called dynamic logic, this type of design uses a clock to synchronize instructions in circuits. This comprehensive book covers the challenges faced by designers when using this logic style, including logic basics, timing, noise considerations, alternative topologies and more. In addition advanced topics such as skew tolerant design are covered in some detail. Overall this is a comprehensive view of precharge logic, which should be useful to graduate students and designers in the field alike. It might also be considered as a supplemental title for courses covering VLSI.
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Professional engineers and students learning about processor and logic design.


Book information

  • Published: August 2012
  • Imprint: ELSEVIER
  • ISBN: 978-0-12-398527-9

Table of Contents

Table of Figures

Table of Tables

1       Precharge Logic Basics

1.1         Introduction

1.2         What is Precharge Logic ?

1.3         Why is it Faster than Static Logic ?

1.4         Advantages of Precharge Logic

1.5         What About Using Other Transistors ?

1.6         Domino Logic

1.6.1       Need for Monotonic Signals

1.6.2       Domino Logic Gates

1.7         Keepers: Improving the Charge Storage

1.8         Final Comments

2       Timing

2.1         Clock Skew Penalty

2.2         Non Overlapping Clocks

2.3         Hold Time Problem

2.4         Hold Time Solution

2.5         Input Setup Criteria

2.6         Input Hold Criteria

2.7         Precharge Timing

2.8         Skew Tolerant Design

3       Transistor Sizing

3.1         Sizing the Pulldown Stack

3.2         Sizing of the Output Inverter

3.3         Logical Effort

3.4         Sizing of the Keeper Device

3.4.1       PFET Keeper

3.4.2       NFET Keeper

3.4.3       Maximum Leakable NFET Width

3.5         Sizing of the Precharge Device

3.6         Sizing Precharge Gates with Wires

4       Noise Tolerance

4.1         Input Connected Prechargers

4.2         Propagated Noise

4.3         Input Wire Noise

4.4         Supply Level Variations

4.5         Charge Sharing

4.6         Example of Charge Sharing

4.7         Charge Sharing Example #2

4.8         Leakage

4.9         Clock Coupling on the Internal Dynamic Node

4.10       Minority Carrier Charge Injection

4.11       Alpha Particles

4.12       Noise Induced on Dynamic Nodes Directly

4.13       Example of Transistor Crosstalk During Precharge

4.14       CSR Latch Signal Ordering

4.15       Interfacing to Transmission Gates

5       Topology Considerations

5.1         Limitation on Device Stacking

5.2         Limitation of Logic Width

5.3         Use of Low/High Vt Transistors

5.4         Sharing Evaluation Devices

5.5         Tapering of the Evaluation Device

5.6         Footed vs Unfooted

5.7         Compounding Outputs

5.8         Late Arriving Input on Top

5.9         Making Keepers Weak

5.10       Conditional Keepers

5.11       Placement of the Evaluation Device

6       Other Precharge Logic Styles

6.1         MODL

6.2         NORA Logic

6.3         Postcharge Logic

6.4         CD Domino

6.5         NTP Logic

6.6         DCVS Logic

6.7         DCML

6.8         SOI Precharge Logic

6.9         Advanced Work

7       Clocked Set-Reset Latches

7.1         Memory Special Cases

7.2         Building a CSR Latch

7.3         Time Borrowing

7.4         Hold Time Margins

7.4.1       Margin 1

7.4.2       Margin 2

7.5         Mintime

7.6         Alternative Topology

7.7         Making it Fast

7.8         The Other Phase

7.9         Two Input Latch

7.10       Multiplexing the Output

7.10.1         Bypass Multiplexer

7.10.2         RAM Redundancy

7.11       Adding Scan

8       Layout Considerations

9       Appendix: Logical Effort 101

9.1         Derivation of Delay in a Logic Gate

9.2         The Logical Effort of a Single Stage

9.3         Multistage Networks

9.4         Minimum Delay

9.5         Best Number of Stages

10           References