Skew-Tolerant Circuit DesignBy
- David Harris, Associate Professor of Engineering, Harvey Mudd College
As advances in technology and circuit design boost operating frequencies of microprocessors, DSPs and other fast chips, new design challenges continue to emerge. One of the major performance limitations in today's chip designs is clock skew, the uncertainty in arrival times between a pair of clocks. Increasing clock frequencies are forcing many engineers to rethink their timing budgets and to use skew-tolerant circuit techniques for both domino and static circuits. While senior designers have long developed their own techniques for reducing the sequencing overhead of domino circuits, this knowledge has routinely been protected as trade secret and has rarely been shared. Skew-Tolerant Circuit Design presents a systematic way of achieving the same goal and puts it in the hands of all designers.
This book clearly presents skew-tolerant techniques and shows how they address the challenges of clocking, latching, and clock skew. It provides the practicing circuit designer with a clearly detailed tutorial and an insightful summary of the most recent literature on these critical clock skew issues.
Paperback, 300 Pages
Published: May 2000
Imprint: Morgan Kaufmann
"Harris leads the way to more performance with a clear strategy for design. He shows how to combine logic and latching to do more logic in less time. In an era where less stuff means higher speed, everyone interested in high performance logic must understand these techniques or be left behind."
Ivan Sutherland, Vice President and Fellow, Sun Microsystems
"The author thoroughly explains important circuit design techniques including various types of latch design styles, clocking strategies, and methods of accounting for clock skew. That all of this is captured in one place is one of the great strengths of this book."
Emily J. Shriver, Alpha Development Group, Compaq Computer Corporation
- CHAPTER 1 - SKEW-TOLERANT CIRCUIT DESIGN1.1 Overhead in Flip-Flop Systems1.2 Throughput and Latency Trends1.2.1 Impact of Overhead on Throughput and Latency1.2.2 Historical Trends1.2.3 Future Predictions1.2.4 Conclusions1.3 Skew-Tolerant Static Circuits1.4 Domino Circuits1.4.1 Domino Gate Operation1.4.2 Traditional Domino Clocking1.4.3 Skew-Tolerant domino1.5 Case Studies1.5.1 Sequencing Overhead in a Static ASIC1.5.2 Sequencing Overhead in the Alpha 211641.5.3 Timing Analysis with Clock Skew1.6 A Look AheadCHAPTER 2 - STATIC CIRCUITS2.1 Preliminaries2.1.1 Purpose of Memory Elements2.1.2 Terminology2.2 Static Memory Elements2.2.1 Timing Diagrams2.2.2 Sequencing Overhead2.2.3 Time Borrowing2.2.4 Min-Delay2.3 Memory Element Design2.3.1 Transparent Latches2.3.2 Pulsed Latches2.3.3 Flip-Flops2.4 Historical Perspective2.5 SummaryCHAPTER 3 - DOMINO CIRCUITS3.1 Skew-Tolerant Domino Timing3.1.1 General Timing Constraints3.1.2 Clock Domains3.1.3 50% Duty Cycle3.1.4 Single Gate per Phase3.1.5 Min-Delay Constraints3.1.6 Recommendations and Design Issues3.2 Domino Gate Design3.2.1 Monotonicity and Dual-Rail Domino3.2.2 Footed and Unfooted Gates3.2.3 Keeper Design3.2.4 Robustness Issues3.3 Historical Perspective3.4 SummaryCHAPTER 4 - CIRCUIT METHODOLOGY4.1 Static/Domino Interface4.1.1 Latch Placement4.1.2 Static to Domino Interface4.1.3 Domino to Static Interface4.1.4 Timing Types4.1.5 Qualified Clocks4.1.6 Min-Delay Checks4.2 Clocked Element Design4.2.1 Latch Design4.2.2 Domino Gate Design4.2.3 Special Structures4.3 Testability4.3.1 Static Logic4.3.2 Domino Logic4.4 Historical Perspective4.5 SummaryCHAPTER 5 - CLOCKING5.1 Clock Waveforms5.1.1 Physical Clock Definitions5.1.2 Clock Skew 5.1.3 Clock Domains5.2 Skew-Tolerant Domino Clock Generation5.2.1 Delay Line Clock Generators5.2.2 Feedback Clock Generators5.2.3 Putting It All Together5.3 SummaryCHAPTER 6 - TIMING ANALYSIS6.1 Timing Analysis without Clock Skew6.2 Timing Analysis with Clock Skew6.2.1 Single Skew Formation6.2.2 Exact Skew Formation6.2.3 Clock Domain Formulation6.2.4 Example6.3 Extension to Flip-Flops and Domino Circuits6.3.1 Flip-Flops6.3.2 Domino Gates6.4 Min-Delay6.5 A Verification Algorithm6.6 Results6.7 Historical Perspective6.8 Summary6.8.1 Skewless Formulation6.8.2 Single Skew Formulation6.8.3 Exact Formulation6.8.4 Clock Domain Formulation6.9 Appendix: Timing ConstraintsCHAPTER 7 - CONCLUSIONSBIBLIOGRAPHY