See MIPS Run book cover

See MIPS Run

This second edition is not only a thorough update of the first edition, it is also a marriage of the best-known RISC architecture--MIPS--with the best-known open-source OS--Linux. The first part of the book begins with MIPS design principles and then describes the MIPS instruction set and programmers’ resources. It uses the MIPS32 standard as a baseline (the 1st edition used the R3000) from which to compare all other versions of the architecture and assumes that MIPS64 is the main option. The second part is a significant change from the first edition. It provides concrete examples of operating system low level code, by using Linux as the example operating system. It describes how Linux is built on the foundations the MIPS hardware provides and summarizes the Linux application environment, describing the libraries, kernel device-drivers and CPU-specific code. It then digs deep into application code and library support, protection and memory management, interrupts in the Linux kernel and multiprocessor Linux. Sweetman has revised his best-selling MIPS bible for MIPS programmers, embedded systems designers, developers and programmers, who need an in-depth understanding of the MIPS architecture and specific guidance for writing software for MIPS-based systems, which are increasingly Linux-based.

Audience
Embedded systems designers and programmers

Paperback, 512 Pages

Published: October 2006

Imprint: Morgan Kaufmann

ISBN: 978-0-12-088421-6

Reviews

  • This book is a worhtwhile read for anyone interested in Linux on MIPS processors or even MIPS and RISC architecture in general.- James Mohr, Linux Magazine, April 2007

Contents

  • Chapter 1: RISCs and MIPS1.1 Pipelines 1.2 The MIPS Five-Stage Pipeline 1.3 RISC and CISC 1.4 Great MIPS Chips of the Past and Present1.5 MIPS Compared with CISC ArchitecturesChapter 2: MIPS Architecture2.1 A Flavor of MIPS Assembly Language2.2 Registers2.3 Integer Multiply Unit and Registers 2.4 Loading and Storing: Addressing Modes 2.5 Data Types in Memory and Registers2.6 Synthesized Instructions in Assembly Language 2.7 MIPS I to MIPS64 ISAs: 64-Bit (and Other) Extensions2.8 Basic Address Space2.9 Pipeline VisibilityChapter 3: Coprocessor 0: MIPS Processor Control3.1 CPU Control Instructions 3.2 What Registers Are Relevant When? 3.3 CPU Control Registers and their encoding3.4 CP0 Hazards—A Trap for the UnwaryChapter 4: How Caches work on MIPS4.1 Caches and Cache Management 4.2 How Caches Work 4.3 Write-Through Caches in Early MIPS CPUs 4.4 Write-Back Caches in MIPS CPUs 4.5 Other Choices in Cache Design 4.6 Managing Caches 4.7 L2 and L3 caches 4.8 Cache Configurations for MIPS CPUs 4.9 Programming MIPS32/64 Caches4.10 Cache Efficiency 4.11 Reorganizing Software to Influence Cache Efficiency 4.12 Cache AliasesChapter 5: Exceptions, Interrupts, and Initialization 5.1 Precise Exceptions 5.2 When Exceptions Happen 5.3 Exception Vectors: Where Exception Handling Starts 5.4 Exception Handling: Basics 5.5 Returning from an Exception 5.6 Nesting Exceptions 5.7 An Exception Routine 5.8 Interrupts5.9 Starting Up5.10 Emulating InstructionsChapter 6: Low-level Memory Management and the TLB 6.1 The TLB/MMU hardware and what it does 6.2 TLB/MMU Registers Described6.3 TLB/MMU Control Instructions 6.4 Programming the TLB6.5 Hardware-friendly page tables and refill mechanism6.6 Everyday Use of the MIPS TLB 6.7 Memory Management in a simpler OSChapter 7: Floating-Point Support 7.1 A Basic Description of Floating Point 7.2 The IEEE754 Standard and Its Background 7.3 How IEEE Floating-Point Numbers Are Stored7.4 MIPS Implementation of IEEE7547.5 Floating-Point Registers7.6 Floating-Point Exceptions/Interrupts 7.7 Floating-Point Control: The Control/Status Register 7.8 Floating-Point Implementation Register 7.9 Guide to FP Instructions7.10 Paired-single floating-point instructions and MIPS 3D.7.11 Instruction Timing Requirements 7.12 Instruction Timing for Speed 7.13 Initialization and Enabling on Demand 7.14 Floating-Point EmulationChapter 8: Complete Guide to the MIPS Instruction Set 8.1 A Simple Example 8.2 Assembler Instructions and What They Mean8.3 Floating-Point Instructions 8.4 Differences in MIPS32/64 Release 18.5 Peculiar Instructions and Their Purposes8.6 Instruction Encodings8.7 Instructions by Functional GroupChapter 9: Reading MIPS Assembler Language 9.1 A Simple Example 9.2 Syntax Overview9.3 General Rules for Instructions9.4 Addressing Modes9.5 Object file and memory layoutChapter 10: Porting Software to MIPS10.1 Low-level software for MIPS: A Checklist of Frequently Encountered Problems 10.2 Endianness: Words, Bytes, and Bit Order10.3 Trouble With Visible Caches10.4 Memory access ordering and re-ordering10.5 Writing it in CChapter 11: MIPS Software Standards (“ABI”s)11.1 Data Representations and Alignment11.2 Argument Passing and Stack Conventions for MIPS “ABIs”Chapter 12: Debugging MIPS - debug and profiling features 12.1 The “EJTAG” onchip debug unit12.2 Pre-EJTAG debug support—break instruction and CP0 Watchpoints 12.3 PDTrace 12.4 Performance countersChapter 13: GNU/Linux from Eight Miles High 13.1 Components 13.2 Layering in the kernelChapter 14: How hardware and software work together 14.1 The life and times of an interrupt 14.2 Threads, critical regions and atomicity14.3 What happens on a system call 38414.4 How addresses get translated in Linux/MIPSChapter 15: MIPS-specific issues in the Linux kernel 15.1 Explicit Cache Management15.2 CP0 Pipeline hazards 15.3 Multiprocessor systems and coherent caches 15.4 Demon tweaks for a Critical RoutineChapter 16 Linux Application Code, PIC and Libraries 16.1 How link units get into a program 16.2 Global Offset Table (“GOT”) organizationAppendix A: MIPS Multithreading A.1 What is MT A.2 Why is MT useful? A.3 How to do MT for a RISC architecture A.4 MT in actionAppendix B: Other Optional extensions to the MIPS instruction set B.1 MIPS16 and MIPS16eB.2 The MIPS DSP ASE 440B.3 MDMXMIPS Glossary

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