Reliability Prediction from Burn-In Data Fit to Reliability Models
- Joseph Bernstein, Ariel University, Ariel, Israel.
This work will educate chip and system designers on a method for accurately predicting circuit and system reliability in order to estimate failures that will occur in the field as a function of operating conditions at the chip level. This book will combine the knowledge taught in many reliability publications and illustrate how to use the knowledge presented by the semiconductor manufacturing companies in combination with the HTOL end-of-life testing that is currently performed by the chip suppliers as part of their standard qualification procedure and make accurate reliability predictions. This book will allow chip designers to predict FIT and DPPM values as a function of operating conditions and chip temperature so that users ultimately will have control of reliability in their design so the reliability and performance will be considered concurrently with their design.
Chip designers, electronic system designers and reliability engineers in electronics companies, chip manufacturers and microelectronics/ system designers