Reconfigurable Computing
The Theory and Practice of FPGA-Based Computation
By- Scott Hauck, Associate Professor, University of Washington, Department of Electrical Engineering, Seattle, WA, U.S.A.
- André DeHon, Assistant Professor, Computer Science, California Institute of Technology, Pasadena, CA, USA.
Audience
Primary: Researchers/Practitioners in Reconfigurable Computing and FPGAs.
Secondary: Graduate-level courses in Advanced Digital Systems (digital design), Reconfigurable Computing, Advanced Computer Architecture, Digital Signal Processing.
Hardbound, 944 Pages
Published: November 2007
Imprint: Morgan Kaufmann
ISBN: 978-0-12-370522-8
Contents
- ContentsPrefaceIntroductionPart One: HardwarePart I INTROChapter 1 - General-Purpose FPGA Architecture Chapter 2 - Reconfigurable Computing DevicesChapter 3 - Reconfigurable Computing SystemsChapter 4 - Reconfiguration ManagementPart Two: SoftwarePart II IntroChapter 5 - Computer Models and System ArchitecturesAndré DeHon Chapter 6 - Hardware Description Languages (VHDL)Chapter 7 - Compilation for Reconfigurable Computing Machines Chapter 8 - Streaming Models8.1 MATLAB/SIMULINK8.2 SCOREChapter 9 SIMD/VectorChapter 10 - OS/Runtime SystemsChapter 11 - JHDLChapter 12 -Technology MappingChapter 13 - Placement13.1 General-purpose / FPGA13.2 Datapath 13.3 ConstructiveChapter 14 - RoutingChapter 15 - RetiminChapter 16 - Bitstream Generation, JBitsChapter 17 - Fast MappingPart Three: Application DevelopmentPART III INTROChapter 18 - Evaluating and Optimizing problems for FPGA implementationsChapter 19- Instance-specific design, Constant Propagation & Partial Evaluation Chapter 20 - Precision Analysis & Floating PointChapter 21 - Distributed ArithmeticChapter 22 - CORDICChapter 23 - Task allocation: FPGA vs. CPU partitioningPart Four: Case StudiesPART IV INTROChapter 24 - Image Processing, Variable Precision, Algorithm Alteration: SPIHT CompressionChapter 25 - Run-time reconfiguration: Automatic Target RecognitionChapter 26 - Problem-specific circuitry: SAT Solving Chapter 27 - Multi-FPGA Systems: Logic EmulationChapter 28- Floating PointChapter 29 - FDTDChapter 30 - Genetic Evolution Chapter 31 - Packet Filtering (Networking application)Chapter 32 - Active Pages [Memory centric]Part Five: Theoretical Underpinnings and Future Directions PART V INTROChapter 33- Theoretical Underpinnings, Metrics and AnalysisChapter 34 - Defect and Fault ToleranceChapter 35 - Reconfigurable Computing and Nanotechnology
