Designing Fast CMOS Circuits
- Ivan Sutherland
- Robert Sproull
- David Harris, Associate Professor of Engineering, Harvey Mudd College, Claremont, CA, USA
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Designers of high-speed integrated circuits face a bewildering array of choices and too often spend frustrating days tweaking gates to meet speed targets. Logical Effort: Designing Fast CMOS Circuits
makes high speed design easier and more methodical, providing a simple and broadly applicable method for estimating the delay resulting from factors such as topology, capacitance, and gate sizes.
The brainchild of circuit and computer graphics pioneers Ivan Sutherland and Bob Sproull, "logical effort" will change the way you approach design challenges. This book begins by equipping you with a sound understanding of the method's essential procedures and concepts-so you can start using it immediately. Later chapters explore the theory and finer points of the method and detail its specialized applications.
This book is intended for anyone who designs CMOS integrated circuits.
- Published: February 1999
- Imprint: MORGAN KAUFMANN
- ISBN: 978-1-55860-557-2
Table of ContentsContents 1 The Method of Logical Effort1.1 Introduction1.2 Delay in a logic gate1.3 Multistage logic networks1.4 Choosing the best number of stages1.5 Summary1.6 Exercises2 Design Examples2.1 The AND function of eight inputs2.1.1 Calculating gate sizes2.2 Decoder2.2.1 Generating complementary inputs2.3 Synchronous arbitration2.3.1 The original circuit2.3.2 Improving the design2.3.3 Restructuring the problem2.4 Summary2.5 Exercises3 Deriving the Method of Logical Effort3.1 Model of a logic gate3.2 Delay in a logic gate3.3 Minimizing delay along a path 3.4 Choosing the length of a path3.5 Using the wrong number of stages3.6 Using the wrong gate size3.7 Summary3.8 Exercises4 Calculating the Logical Effort of Gates4.1 Definitions of logical effort4.2 Grouping input signals4.3 Calculating logical effort4.4 Asymmetric logic gates4.5 Catalog of logic gates4.5.1 NAND gate4.5.2 NOR gate4.5.3 Multiplexers, tristate inverters4.5.4 XOR, XNOR, and parity gates4.5.5 Majority gate4.5.6 Adder carry chain4.5.7 Dynamic latch4.5.8 Dynamic Muller Celement4.5.9 Upper bounds on logical effort4.6 Estimating parasitic delay4.7 Properties of logical effort4.8 Exercises5 Calibrating the Model5.1 Calibration technique5.2 Designing test circuits5.2.1 Rising, falling, and average delays5.2.2 Choice of input5.2.3 Parasitic capacitance5.2.4 Process sensitivity5.3 Other characterization methods5.3.1 Data sheets 5.3.2 Test chips5.4 Calibrating special circuit families5.5 Summary5.6 Exercises6 Asymmetric Logic Gates6.1 Designing asymmetric logic gates6.2 Applications of asymmetric logic gates6.2.1 Multiplexers6.3 Summary6.4 Exercises7 Unequal Rising and Falling Delays7.1 Analyzing delays7.2 Case analysis7.2.1 Skewed gates7.2.2 Impact of fl and ¯ on logical effort7.3 Optimizing CMOS P=N ratios7.4 Summary7.5 Exercises8 Circuit Families8.1 PseudoNMOS circuits8.1.1 Symmetric NOR gates8.2 Domino circuits8.2.1 Logical effort of dynamic gates8.2.2 Stage effort of domino circuits8.2.3 Building logic in static gates8.2.4 Designing dynamic gates8.3 Transmission gates8.4 Summary8.5 Exercises9 Forks of Amplifiers9.1 The fork circuit form9.2 How many stages should a fork use?9.3 Summary9.4 Exercises10 Branches and Interconnect10.1 Circuits that branch at a single input10.1.1 Branch paths with equal lengths10.1.2 Branch paths with unequal lengths10.2 Branches after logic10.3 Circuits that branch and recombine10.4 Interconnect10.4.1 Short wires10.4.2 Long wires10.4.3 Medium wires10.5 A design approach10.6 Exercises11 Wide Structures11.1 An ninput AND structure11.1.1 Minimum logical effort11.1.2 Minimum delay11.1.3 Other wide functions11.2 An ninput Muller Celement11.2.1 Minimum logical effort11.2.2 Minimum delay11.3 Decoders11.3.1 Simple decoder11.3.2 Predecoding11.3.3 LyonSchediwy decoder11.4 Multiplexers11.4.1 How wide should a multiplexer be?11.4.2 Mediumwidth multiplexers11.5 Summary11.6 Exercises12 Conclusions12.1 The theory of logical effort12.2 Insights from logical effort12.3 A design procedure12.4 Other approaches to path design12.4.1 Simulate and tweak12.4.2 Equal fanout12.4.3 Equal delay12.4.4 Numerical optimization12.5 Shortcomings of logical effort12.6 Parting wordsA Cast of CharactersB Reference process parametersC Logical Effort ToolsC.1 Library characterizationC.2 Wide gate designD SolutionsD.1 Chapter 1D.2 Chapter 2D.3 Chapter 3D.4 Chapter 4D.5 Chapter 5D.6 Chapter 6D.7 Chapter 7D.8 Chapter 8D.9 Chapter 9D.10 Chapter 10D.11 Chapter 11