FPGAs: World Class Designs

Edited by

  • Clive Maxfield, Engineer, TechBytes, and Editor of PLDesignline.com EDA industry consultant, EDN columnist, and Embedded Systems Guru

All the design and development inspiration and direction a harware engineer needs in one blockbuster book! Clive "Max" Maxfield renowned author, columnist, and editor of PL DesignLine has selected the very best FPGA design material from the Newnes portfolio and has compiled it into this volume. The result is a book covering the gamut of FPGA design from design fundamentals to optimized layout techniques with a strong pragmatic emphasis. In addition to specific design techniques and practices, this book also discusses various approaches to solving FPGA design problems and how to successfully apply theory to actual design tasks. The material has been selected for its timelessness as well as for its relevance to contemporary FPGA design issues.ContentsChapter 1 Alternative FPGA ArchitecturesChapter 2 Design Techniques, Rules, and GuidelinesChapter 3 A VHDL Primer: The EssentialsChapter 4 Modeling MemoriesChapter 5 Introduction to Synchronous State Machine Design and AnalysisChapter 6 Embedded ProcessorsChapter 7 Digital Signal ProcessingChapter 8 Basics of Embedded Audio ProcessingChapter 9 Basics of Embedded Video and Image ProcessingChapter 10 Programming Streaming FPGA Applications Using Block Diagrams In SimulinkChapter 11 Ladder and functional block programmingChapter 12 Timers
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Electronics Designers and Programmers; Application Engineers; Hardware Engineers; Software Engineers


Book information

  • Published: February 2009
  • Imprint: NEWNES
  • ISBN: 978-1-85617-621-7

Table of Contents

Chapter 1 Alternative FPGA Architectures1.1 A word of warning1.2 A little background information1.3 Antifuse versus SRAM versus …1.4 Fine-, medium-, and coarse-grained architectures1.5 MUX- versus LUT-based logic blocks1.6 CLBs versus LABs versus slices1.7 Fast carry chains1.8 Embedded RAMs1.9 Embedded multipliers, adders, MACs, etc.1.10 Embedded processor cores (hard and soft)1.11 Clock trees and clock managers1.12 General-purpose I/O1.13 Gigabit transceivers1.14 Hard IP, soft IP, and firm IP1.15 System gates versus real gates1.16 FPGA yearsChapter 2 Design Techniques, Rules, and Guidelines2.1 Hardware Description Languages2.2 Top-Down Design2.3 Synchronous Design2.4 Floating Nodes2.5 Bus Contention2.6 One-Hot State Encoding2.7 Design For Test (DFT)2.8 Testing Redundant Logic2.9 Initializing State Machines2.10 Observable Nodes2.11 Scan Techniques2.12 Built-In Self-Test (BIST)2.13 Signature Analysis2.14 SummaryChapter 3 A VHDL Primer: The Essentials3.1 Introduction3.2 Entity: model interface3.3 Architecture: model behavior3.4 Process: basic functional unit in VHDL3.5 Basic variable types and operators3.6 Decisions and loops3.7 Hierarchical design3.8 Debugging models3.9 Basic data types3.10 SummaryChapter 4 Modeling Memories4.1 Memory Arrays4.2 Modeling Memory Functionality4.3 VITAL_Memory Path Delays4.4 VITAL_Memory Timing Constraints4.5 Preloading Memories4.6 Modeling Other Memory Types4.7 SummaryChapter 5 Introduction to Synchronous State Machine Design and Analysis5.1 Introduction5.2 Models For Sequential Machines5.3 The Fully Documented State Diagram5.4 The Basic Memory Cells5.5 Introduction To Flip-Flops5.6 Procdure For FSM (Flip-Flop) Design And The Mapping Algorithm5.7 The D Flip-Flops: General5.8 Flip-Flop Conversion: The T, JK Flip-Flops And Miscellaneous Flip-Flops5.9 Latches And Flip-Flops With Serious Timing Problems: A Warning5.10 Asynchronous Preset And Clear Overrides5.11 Setup And Hold-Time Requirements Of Flip-Flops5.12 Design Of Simple Synchronous State Machines With Edge-Triggered Flip-Flops: Map Conversion5.13 Analysis Of Simple State Machines5.14 VHDL Description Of Simple State Machines5.15 Further ReadingChapter 6 Embedded Processors6.1 Introduction6.2 A simple embedded processor6.3 Soft core processors on an FPGA6.4 SummaryChapter 7 Digital Signal Processing7.1 Overview7.2 Basic DSP System7.3 Essential DSP terms7.4 DSP architectures7.5 parallel execution in DSP Components7.6 parallel execution in FPGA7.7 When to Use FPGAs for DSP7.8 FPGA DSP Design Considerations7.9 FIR Filter Concept Example7.10 SummaryChapter 8 Basics of Embedded Audio Processing8.1 Introduction8.2 Audio Sources and Sinks8.3 Interconnections8.4 Dynamic Range and Precision8.5 Audio Processing Methods8.6 What’s Next?Chapter 9 Basics of Embedded Video and Image Processing9.1 Introduction9.2 Broadcast TV—NTSC and PAL9.3 Color Spaces9.4 Digital Video9.5 A Systems View of Video9.6 Embedded Video processing Considerations9.7 Compression/Decompression9.8 What’s Next?Chapter 10 Programming Streaming FPGA Applications Using Block Diagrams In Simulink10.1 Designing High-Performance Datapaths Using Stream-Based Operators10.2 An Image-Processing Design Driver10.3 Specifying Control In Simulink10.4 Component Reuse: Libraries Of Simple And Complex Subsystems10.5 Summary10.6 ReferencesChapter 11 Ladder and functional block programming11.1 Ladder diagrams11.2 Logic functions11.3 Latching11.4 Multiple outputs11.5 Entering programs11.6 Function blocks11.7 Program examples11.8 ProblemsChapter 12 Timers12.1 Types of timers12.2 Programming timers12.3 Off-delay timers12.4 Pulse timers12.5 Programming examples12.6 Problems