ESL Design and Verification

A Prescription for Electronic System Level Methodology

  • Mark Burton
    • Jack Greenbaum
      • Kamal Hashmi
        • Anssi Haverinen
          • Luciano Lavagno
            • Michael Meredith
              • Bill Murray
                • Ian Oliver
                  • Claudio Passerone
                    • John Sanguinetti
                      • Florian Schaefer
                      • By

                        • Grant Martin, Tensilica, Inc., Pleasanton, CA
                        • Brian Bailey, Poseidon Design Systems, Oregon City, OR
                        • Andrew Piziali, Cadence Design Systems, Parker, TX

                        Visit the authors' companion site! - Includes interactive forum with the authors!Electronic System Level (ESL) design has mainstreamed – it is now an established approach at most of the world’s leading system-on-chip (SoC) design companies and is being used increasingly in system design. From its genesis as an algorithm modeling methodology with ‘no links to implementation’, ESL is evolving into a set of complementary methodologies that enable embedded system design, verification and debug through to the hardware and software implementation of custom SoC, system-on-FPGA, system-on-board, and entire multi-board systems. This book arises from experience the authors have gained from years of work as industry practitioners in the Electronic System Level design area; they have seen "SLD" or "ESL" go through many stages and false starts, and have observed that the shift in design methodologies to ESL is finally occurring. This is partly because of ESL technologies themselves are stabilizing on a useful set of languages being standardized (SystemC is the most notable), and use models are being identified that are beginning to get real adoption. ESL DESIGN & VERIFICATION offers a true prescriptive guide to ESL that reviews its past and outlines the best practices of today.Table of ContentsCHAPTER 1: WHAT IS ESL? CHAPTER 2: TAXONOMY AND DEFINITIONS FOR THE ELECTRONIC SYSTEM LEVEL CHAPTER 3: EVOLUTION OF ESL DEVELOPMENT CHAPTER 4: WHAT ARE THE ENABLERS OF ESL? CHAPTER 5: ESL FLOW CHAPTER 6: SPECIFICATIONS AND MODELING CHAPTER 7: PRE-PARTITIONING ANALYSIS CHAPTER 8: PARTITIONING CHAPTER 9: POST-PARTITIONING ANALYSIS AND DEBUG CHAPTER 10: POST-PARTITIONING VERIFICATION CHAPTER 11: HARDWARE IMPLEMENTATION CHAPTER 12: SOFTWARE IMPLEMENTATION CHAPTER 13: USE OF ESL FOR IMPLEMENTATION VERIFICATION CHAPTER 14: RESEARCH, EMERGING AND FUTURE PROSPECTS APPENDIX: LIST OF ACRONYMS
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                        PRIMARY: Industry practitioners; SOC engineers designing embedded systems
 System architect, (MP)SoC system designer, Engineering managers in the (MP)SoC system design field.


Book information

  • Published: February 2007
  • ISBN: 978-0-12-373551-5

Table of Contents

CHAPTER 1 WHAT IS ESL? So, What is ESL?Who Should Read this BookChapter ListingThe PrescriptionReferences CHAPTER 2 TAXONOMY AND DEFINITIONS FOR THE ELECTRONIC SYSTEM LEVELTaxonomyIntroductionModel TaxonomyTemporal AxisData AxisFunctionality AxisStructural AxisESL TaxonomyConcurrencyCommunication Concurrency and CommunicationsConfigurabilityExamplesLanguagesProcessorsFlowsDefinitionsAcronymsCHAPTER 3 EVOLUTION OF ESL DEVELOPMENTIntroductionMotivation for ESL DesignTraditional System Design EffectivenessSystem Design with ESL MethodologyBehavioural Modelling MethodologyVSP: Potential ValueVSP: Programmer’s ViewVSP: Programmer’s View Plus TimingVSP: Cycle Accurate ViewBehavioural Modelling EnvironmentsCommercial ToolsThe Trailblazer: VCCLatest Generation ToolsPOLISPtolemy SimulatorSpecC LanguageOSCI SystemC Reference SimulatorHistorical Barriers to Adoption of Behavioural Modelling The Demand SideThe Standards BarrierOpen SystemC InitiativeOpen Core Protocol International PartnershipSpecC Technology Open ConsortiumThe System Level Language WarAutomated Links to Chip ImplementationAutomated Implementation of Fixed-Function Hardware Commercial ToolsMathematical Algorithm Development ToolsGraphical Algorithm Development ToolsThe Trailblazer: Behavioral CompilerLatest Generation High-Level Synthesis ToolsOpen Source and Academic ToolsSPARK Parallelising High Level Synthesis (PHLS)Automated Implementation of Programmable Hardware Processor Design Using EDA ToolsProcessor Designer and Chess/CheckersCriticalBlue Cascade Coprocessor SynthesisProcessor Design Using IP-Based MethodsConfigurable IP: Tensilica Xtensa and ARC 600/700IP Assembly: ARM OptimoDEMainstreaming ESL MethodologyWho Bears the Risk?Adoption by System ArchitectsAcceptance by RTL TeamsBehavioural Modelling IDEsASIP Processor DesignEffect of ESL on EDA Tool SeatsESL and the Big 3 Three CompaniesThe PrescriptionReferencesCHAPTER 4 WHAT ARE THE ENABLERS OF ESL?IntroductionTool and Model LandscapeSystem Designer RequirementsAccuracyTime and SpeedTraffic Generator Models Tool Cost and Value PropositionSoftware Team RequirementsAccuracyRegister AccuracyCycle Count AccuracyConcurrent and State AccuracyModel Creation TimeModel Execution PerformanceTool Chain CostHardware Team RequirementsModel RefinementVerification Environment ProvisionVerificationVerification SimulationCostWho Will Service These Diverse Requirements? Free or Open Source SoftwareF/OSS Community and Quality EffectsF/OSS LicensesCopyright OwnershipLicense TermsOSCI’s LicenseLicense CompatibilityThe Scope of F/OSS Within ESLDirect BenefitsOther Effects of F/OSSEnabling (Academic) ResearchEconomics of F/OSS Business ModelsSummaryReferencesCHAPTER 5 ESL FLOWIntroductionSpecifications and ModellingPre-Partitioning AnalysisPartitioningPost-Partitioning Analysis and DebugPost-Partitioning VerificationHardware ImplementationUse of ESL for Implementation VerificationProvocative ThoughtsSummaryThe PrescriptionCHAPTER 6 SPECIFICATIONS AND MODELLINGIntroductionThe Problem of SpecificationThe Implementation and Ambiguity ProblemsThe Heterogeneous Technology and Single-Source ProblemsArchitectures, Attributes and BehaviourFormal and Executable Specifications and ModellingCase Study: Requirements Management Process at Vandelay IndustriesESL Domains Dataflow and Control flowProtocol StacksEmbedded SystemsExecutable SpecificationsTransaction Level Modelling and Executable SpecificationsExecutable Specifications and the Single-Source ProblemSome ESL Languages for SpecificationMATLABRosettaSystemCSystemVerilogSDLThe UMLXMLBluespecAspect Oriented LanguagesProvocative Thoughts: Model Based DevelopmentModel Driven Architecture Software/Hardware Co-DesignHardwareHow to Use MDDSummaryThe PrescriptionReferencesCHAPTER 7 PRE-PARTITIONING ANALYSISIntroductionStatic Analysis of System SpecificationsThe Software Project Estimation Heritage—Function Point AnalysisAnalysis of Hardware and Hardware-Dominated System SpecificationsTraditional “ility” Analysis of SystemsRequirements AnalysisNew Specification Methods – RosettaConclusions on Static AnalysisThe Role of Platform-Based ESL Design in Pre-Partitioning AnalysisDynamic AnalysisAlgorithmic AnalysisCommercial Tools for Algorithmic AnalysisResearch ToolsAnalysis Scenarios and ModellingExample of Analysis of Signal Processing AlgorithmsFilter Design ExampleComplete System Specification to Silicon Methodology for Communications and Multimedia Signal ProcessingSoftware Radio ExampleHow Much Analysis is Enough?Downstream Use of Analysis ResultsCase Study – JPEG EncodingSummary and Provocative ThoughtsThe Prescription for Pre-Partitioning AnalysisReferencesCHAPTER 8 PARTITIONINGIntroductionFunctional DecompositionArchitecture DescriptionPlatformsArchitectural ComponentsModelling LevelsPartitioningRefinement Based MethodsSystem Scheduling and Constraint SatisfactionThe Hardware PartitionModule Refinement The Software PartitionPartitioning Over Multiple ProcessorsPartitioning over Multiple TasksWorst-Case Execution Time AnalysisThe Operating SystemCommercial Operating SystemsCustom Operating SystemsMemory PartitioningReconfigurable ComputingReconfigurable Computing ArchitecturesDynamic Online PartitioningCommunication ImplementationInterface Template InstantiationInterface SynthesisProvocative ThoughtsSummaryThe PrescriptionReferencesCHAPTER 9 POST-PARTITIONING ANALYSIS AND DEBUGIntroductionRoles and ResponsibilitiesHardware and Software Modelling and Co-ModellingSingle ModelSeparate Model: Filtered/TranslatedSeparate Hosted ModelModelling Infrastructure and Inter-Model ConnectionsPartitioned Systems and Re-PartitioningPre-Partitioned Model ComponentsAbstraction LevelsStandardising Abstraction Levels for InteroperabilityMoving Between Abstraction LevelsCommunication SpecificationDynamic and Static AnalysesMetrics and the Importance of ExperienceFunctional AnalysisPerformance AnalysisInterface AnalysisPower AnalysisArea AnalysisCost Analysis Debug Capability AnalysisObservabilityControllabilityCorrectabilityProvocative Thoughts SummaryThe PrescriptionCHAPTER 10 POST-PARTITIONING ANALYSIS AND VERIFICATIONIntroductionFacets of VerificationVerification PlanningWhat is the Scope of the Verification Problem?Specification AnalysisBottom-Up Specification AnalysisTop-Down Specification AnalysisCoverage Model Top Level DesignCoverage Model Detailed DsignHybrid Metric Coverage ModelsWhat is the Solution to the Verification Problem?Stimulus GenerationResponse CheckingVerification Planning AutomationVerification Environment ImplementationWrite Verification EnvironmentFailure AnalysisCoverage AnalysisAbstract CoverageOther ApproachesTurning the TablesMutation AnalysisThe Role of PrototypingPlatform VerificationProvocative ThoughtsSummaryThe PrescriptionCHAPTER 11 HARDWARE IMPLEMENTATIONIntroductionExtensible ProcessorsDSP Co-processorsCustomised VLIW Co-ProcessorsApplication Specific Co-ProcessorsHigh-level Hardware Design Flow for ASIC and FPGABehavioural SynthesisDifferences between RTL and Behavioural CodeMulticycle FunctionalityLoopsMemory AccessBehavioural Synthesis Shortcomings: Input LanguageBehavioural Synthesis Shortcomings: TimingBehavioural Synthesis Shortcomings: VerificationESL SynthesisLanguageStructureConcurrencyData typesOperationsExampleInput and OutputVerificationTimingSchedulingAllocationBack-end FriendlinessExample ResultsHardware Design or Silver Bullet?Role of ConstraintsPragmasCode ChangesExampleConstraintsCode ModificationDesign ExplorationProvocative ThoughtsSummaryThe PrescriptionReferencesCHAPTER 12 SOFTWARE IMPLEMENTATION IntroductionClassical Software Development Methods for Embedded Systems and SoCsPerformance EstimationClassical Development ToolsDeveloping Run-Time Software from ESL ModelsUML Code Generation Case StudyDeveloping Software Using ESL Models as Run-Time Environments Classes of ESL Models for Software DevelopmentObservability for Debug and AnalysisSoftware Debug and Analysis Tools for Highly Observable SystemsSummaryProvocative ThoughtsThe PrescriptionReferencesCHAPTER 13 USE OF ESL FOR IMPLEMENTATION VERIFICATIONWhat This Chapter is Not AboutPositive and Negative VerificationVerification FocusClear Box VerificationVerification IPDynamic Verification IPAssertion LibrariesProperties and AssertionsAssertionsFormal MethodsStarting StateLimiting the FutureSpeeding Up the DesignLimiting StatesCoverageSystem VerificationPost-Silicon DebugObservability and DebugInternal Logic AnalyserDynamic ModificationsProvocative ThoughtsSequential Equivalence CheckingProperty-Based DesignSummaryThe PrescriptionCHAPTER 14 RESEARCH, EMERGING AND FUTURE PROSPECTSResearch MetropolisSpaceMultiple ProcessorsEmerging ArchitecturesROSESGlobalisationValue MigrationEducationThe Academic ViewThe Health of the Commercial EDA IndustrySummaryThe Prescription