Engineering Digital Design book cover

Engineering Digital Design

Revised Second Edition

Engineering Digital Design, Second Edition provides the most extensive coverage of any available textbook in digital logic and design. The new REVISED Second Edition published in September of 2002 provides 5 productivity tools free on the accompanying CD ROM. This software is also included on the Instructor's Manual CD ROM and complete instructions accompany each software program.In the REVISED Second Edition modern notation combines with state-of-the-art treatment of the most important subjects in digital design to provide the student with the background needed to enter industry or graduate study at a competitive level. Combinatorial logic design and synchronous and asynchronous sequential machine design methods are given equal weight, and new ideas and design approaches are explored. The productivity tools provided on the accompanying CD are outlined below:[1] EXL-Sim2002 logic simulator: EXL-Sim2002 is a full-featured, interactive, schematic-capture and simulation program that is ideally suited for use with the text at either the entry or advanced-level of logic design. Its many features include drag-and-drop capability, rubber banding, mixed logic and positive logic simulations, macro generation, individual and global (or randomized) delay assignments, connection features that eliminate the need for wire connections, schematic page sizing and zooming, waveform zooming and scrolling, a variety of printout capabilities, and a host of other useful features. [2] BOOZER logic minimizer: BOOZER is a software minimization tool that is recommended for use with the text. It accepts entered variable (EV) or canonical (1's and 0's) data from K-maps or truth tables, with or without don't cares, and returns an optimal or near optimal single or multi-output solution. It can handle up to 12 functions Boolean functions and as many inputs when used on modern computers. [3] ESPRESSO II logic minimizer: ESPRESSO II is another software minimization tool widely used in schools and industry. It supports advanced heuristic algorithms for minimization of two-level, multi-output Boolean functions but does not accept entered variables. It is also readily available from the University of California, Berkeley, 1986 VLSI Tools Distribution. [4] ADAM design software: ADAM (for Automated Design of Asynchronous Machines) is a very powerful productivity tool that permits the automated design of very complex asynchronous state machines, all free of timing defects. The input files are state tables for the desired state machines. The output files are given in the Berkeley format appropriate for directly programming PLAs. ADAM also allows the designer to design synchronous state machines, timing-defect-free. The options include the lumped path delay (LPD) model or NESTED CELL model for asynchronous FSM designs, and the use of D FLIP-FLOPs for synchronous FSM designs. The background for the use of ADAM is covered in Chapters 11, 14 and 16 of the REVISED 2nd Edition.[5] A-OPS design software: A-OPS (for Asynchronous One-hot Programmable Sequencers) is another very powerful productivity tool that permits the design of asynchronous and synchronous state machines by using a programmable sequencer kernel. This software generates a PLA or PAL output file (in Berkeley format) or the VHDL code for the automated timing-defect-free designs of the following: (a) Any 1-Hot programmable sequencer up to 10 states. (b) The 1-Hot design of multiple asynchronous or synchronous state machines driven by either PLDs or RAM. The input file is that of a state table for the desired state machine. This software can be used to design systems with the capability of instantly switching between several radically different controllers on a time-shared basis. The background for the use of A-OPS is covered in Chapters 13, 14 and 16 of the REVISED 2nd Edition.The above software, as bundled with the REVISED 2nd Edition, will be unique and highly useful to students and faculty alike for both instructional and research purposes. All of the above software, except the EXL-Sim2002 simulator, require the use of a text editor. A "Slideshow" and a "Software Overview" are also included on the CD ROM to provide additional information regarding these productivity tools and the many other new and unique features found in Engineering Digital Design REVISED Second Edition). Other new features found in the REVISED Second Edition include numerous new end-of-chapter problems that have been added to enrich the student's learning experience by making use of the software tools listed above. After inspecting the REVISED Second Edition and using the software bundled with it readers will find a fresh new approach to logic design and analysis has been introduced. The text is designed to be used at the entry, intermediate or advanced levels thereby making it unnecessary for students to change texts between successive courses in the subject area.

Audience
This comprehensive textbook can be utilized in both beginning and intermediate courses in electrical and computer engineering. The book will also provide an invaluable source of information for graduate students and for engineers in industry.

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Published: January 2000

Imprint: Academic Press

ISBN: 978-0-12-691295-1

Contents

  • Preface.Introductory Remarks and Glossary.Number Systems, Binary Arithmetic, and Codes.Background for Digital Design.Logic Function Representation and Minimization.Function Minimization by Using K-map XOR Patterns and Reed-Muller Transformation Forms.Nonarithmetic Combinational Logic Devices.Programmable Logic Devices.Arithmetic Devices and Arithmetic Logic Units (ALUs).Propagation Delay and Timing Defects in Combinational Logic.Introduction to Synchronous State Machine Design and Analysis.Synchronous FSM Design Considerations and Applications.Module and Bit-Slice Devices.Alternative Synchronous FSM Architectures and Systems-Level Design.Asynchronous State Machine Design and Analysis: Basic Concepts.The Pulse Mode Approach to Asynchronous FSM Design.Externally Asynchronous/Internally Clocked (Pausable) Systems and Programmable Asynchronous Sequencers.Other Transistor Logic Families.Computer-Aided Engineering Tools.IEEE Standard Symbols.Index.

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