Embedded DSP Processor Design book cover

Embedded DSP Processor Design

Application Specific Instruction Set Processors

This book provides design methods for Digital Signal Processors and Application Specific Instruction set Processors, based on the author's extensive, industrial design experience. Top-down and bottom-up design methodologies are presented, providing valuable guidance for both students and practicing design engineers. Coverage includes design of internal-external data types, application specific instruction sets, micro architectures, including designs for datapath and control path, as well as memory sub systems. Integration and verification of a DSP-ASIP processor are discussed and reinforced with extensive examples. FOR INSTRUCTORS: To obtain access to the solutions manual for this title simply register on our textbook website (textbooks.elsevier.com)and request access to the Computer Science or Electronics and Electrical Engineering subject area. Once approved (usually within one business day) you will be able to access all of the instructor-only materials through the ";Instructor Manual"; link on this book's full web page.

Audience
Designers of application specific, embedded digital signal processors at companies such as Ericsson, Infineon, ST Microelectronics, Analog Devices, Philips, Siemens, Texas Instruments, Broadcom, Qualcom, AGilent, NEC, Intel, AMD, Fujitsu, Sony, Toshiba, Sanyo, Samsung, etc; EE students studying to be same.

Included in series
Systems on Silicon

Hardbound, 808 Pages

Published: May 2008

Imprint: Morgan Kaufmann

ISBN: 978-0-12-374123-3

Contents

  • Introduction to DSP and CPU; Finite length DSP; Architecture and Micro architecture design; Instruction set design ? part I; Instruction set design ? part II; ALU and Register file (RF); MAC (Multiplication and accumulation unit); Memory sub system and addressing unit; Control path; Design of tools for firmware programmers; Firmware design; Peripheral of DSP cores and processors; Accelerators; Advanced architecture ILP (Instruction level parallelism); Advanced architecture (On Chip multiple DSP cores); Design for integration; Review of the design flow and functional verification

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