Digital Design and Computer Architecture


  • David Harris, Associate Professor of Engineering, Harvey Mudd College, Claremont, CA, USA
  • Sarah Harris, Assistant Professor of Engineering, Harvey Mudd College, Claremont, CA, USA

Digital Design and Computer Architecture is designed for courses that combine digital logic design with computer organization/architecture or that teach these subjects as a two-course sequence. Digital Design and Computer Architecture begins with a modern approach by rigorously covering the fundamentals of digital logic design and then introducing Hardware Description Languages (HDLs). Featuring examples of the two most widely-used HDLs, VHDL and Verilog, the first half of the text prepares the reader for what follows in the second: the design of a MIPS Processor. By the end of Digital Design and Computer Architecture, readers will be able to build their own microprocessor and will have a top-to-bottom understanding of how it works--even if they have no formal background in design or architecture beyond an introductory class. David Harris and Sarah Harris combine an engaging and humorous writing style with an updated and hands-on approach to digital design.
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students taking a course that combines digital logic and computer architecture or students taking a two-quarter sequence in digital logic and computer organization/architecture


Book information

  • Published: March 2007
  • ISBN: 978-0-12-370497-9

Table of Contents

Table of Contents1 From Zero to One1.1 The Game Plan1.2 The Art of Managing Complexity 1.3 The Digital Abstraction 1.4 Number Systems1.5 Logic Gates 1.6 Logic Levels 1.7 * CMOS Transistors1.8 * Power Consumption 1.9 Summary and A Look Ahead 2 Combinational Logic Design2.1 Introduction2.2 Boolean Equations 2.3 Boolean Algebra2.4 From Logic to Gates 2.5 Multilevel Combinational Logic 2.6 X's and Z's, Oh My 2.7 Karnaugh Maps 2.8 Combinational Building Blocks2.9 Timing 2.10 Summary3 Sequential Logic Design 3.1 Introduction3.2 Latches and Flip-Flops 3.3 Synchronous Logic Design 3.4 Finite State Machines 3.5 Timing of Sequential Logic 3.6 Parallelism3.7 Summary4 Hardware Description Languages4.1 Introduction4.2 Combinational Logic 4.3 Structural Modeling 4.4 Sequential Logic4.5 More Combinational Logic 4.6 Finite State Machines 4.7 * Parameterized Modules4.8 Testbenches4.9 Summary5 Digital Building Blocks 5.1 Introduction5.2 Arithmetic Circuits 5.3 Number Systems 5.4 Sequential Building Blocks 5.5 Memory Arrays5.6 Logic Arrays5.7 Summary6 Architecture 6.1 Introduction6.2 Assembly Language 6.3 Machine Language6.4 Programming 6.5 Addressing Modes6.6 Lights, Camera, Action: Compiling, Assembling, and Loading6.7 * Odds and Ends 6.8 * Real World Perspective: IA-32 Architecture 6.9 Summary7 Microarchitecture7.1 Introduction7.2 Performance Analysis7.3 Single-Cycle Processor 7.4 Multicycle Processor7.5 Pipelined Processor7.6 * HDL Representation7.7 * Exceptions7.8 * Advanced Microarchitecture 7.9 * Real World Perspective: IA-32 Microarchitecture7.10 Summary8 Memory Systems 8.1 Introduction8.2 Memory System Performance Analysis8.3 Caches 8.4 Virtual Memory 8.5 * Memory-Mapped I/O 8.6 * Real World Perspective: IA-32 Memory and I/O Systems 8.7 SummaryAppendix A Digital System Implementation A.1 IntroductionA.2 74xx Logic A.3 Programmable Logic A.4 Application-Specific Integrated Circuits A.5 Data Sheets A.6 Logic FamiliesA.7 Packaging and AssemblyA.8 Transmission linesA.9 Economics Appendix B MIPS Instructions