Design Recipes for FPGAs: Using Verilog and VHDL book cover

Design Recipes for FPGAs: Using Verilog and VHDL

This book provides a rich toolbox of design techniques and templates to solve practical, every-day problems using FPGAs. Using a modular structure, the book gives ‘easy-to-find’ design techniques and templates at all levels, together with functional code, which engineers can easily match and apply to their application.

The ‘easy-to-find’ structure begins with a design application to demonstrate the key building blocks of FPGA design and how to connect them, enabling the experienced FPGA designer to quickly select the right design for their application, while providing the less experienced a ‘road map’ to solving their specific design problem.

Written in an informal and ‘easy-to-grasp’ style, this invaluable resource goes beyond the principles of FPGA s and hardware description languages to actually demonstrate how specific designs can be synthesized, simulated and downloaded onto an FPGA. In addition, the book provides advanced techniques to create ‘real world’ designs that fit the device required and which are fast and reliable to implement. An accompanying companion website contains code, test benches and simulation command files for ModelSim.

This book will be an indispensable, well-thumbed resource for FPGA designers of all levels of experience.

Audience
Embedded system development engineers, FPGA engineers, hardware and software engineers. Undergraduates and postgraduates studying an embedded system which focuses on FPGA design.

Paperback, 320 Pages

Published: May 2007

Imprint: Newnes

ISBN: 978-0-7506-6845-3

Reviews

  • "Design Recipes for FPGAs is an excellent volume for engineers who work with FPGAs either regularly or occasionally... the book provides a handy shelf reference with examples for many useful functional blocks, ranging from relatively small illustrative syntactic and structural examples to more complex concepts. Whether you work in VHDL occasionally or every day, you'll find practical help in this book." - Lewin Edwards, Design Engineer and Technical Author

Contents

  • ACKNOWLEDGEMENTSPREFACETABLE OF CONTENTSTABLE OF FIGURESSECTION 1: INTRODUCTIONCHAPTER 1: INTRODUCTION1.1 OVERVIEW1.2 WHY FPGAS?CHAPTER 2: AN FPGA PRIMER2.1 INTRODUCTION2.2 FPGA EVOLUTION2.3 PROGRAMMABLE LOGIC DEVICES2.4 FIELD PROGRAMMABLE GATE ARRAYS2.5 FPGA DESIGN TECHNIQUES2.6 DESIGN CONSTRAINTS USING FPGAS2.7 SUMMARYCHAPTER 3: A VHDL PRIMER – THE ESSENTIALS3.1 INTRODUCTION 3.2 ENTITY – MODEL INTERFACE3.3 ARCHITECTURE – MODEL BEHAVIOUR3.4 PROCESS – BASIC FUNCTIONAL UNIT IN VHDL 3.5 BASIC VARIABLE TYPES AND OPERATORS3.6 DECISIONS AND LOOPS3.7 HIERARCHICAL DESIGN3.8 DEBUGGING MODELS3.9 BASIC DATA TYPES3.10 SUMMARYCHAPTER 4: DESIGN AUTOMATION AND TESTING FOR FPGAS4.1 SIMULATION4.2 LIBRARIES4.3 SYNTHESIS4.4 PHYSICAL DESIGN FLOW4.5 PLACE AND ROUTE 4.6 TIMING ANALYSIS4.7 DESIGN PITFALLS4.8 VHDL ISSUES FOR FPGA DESIGN4.9 SUMMARY SECTION 2: APPLICATIONSCHAPTER 5: INTRODUCTIONCHAPTER 6: IMAGES AND HIGH SPEED PROCESSING6.1 INTRODUCTION6.2 THE CAMERA LINK INTERFACE6.3 GETTING STARTED6.4 SPECIFYING THE INTERFACES6.5 DEFINING THE TOP LEVEL DESIGN6.6 SYSTEM BLOCK DEFINITIONS AND INTERFACES6.7 THE CAMERALINK INTERFACE6.8 THE HARD DISC INTERFACE6.9 SUMMARY CHAPTER 7: EMBEDDED PROCESSORS7.1 INTRODUCTION7.2 A SIMPLE EMBEDDED PROCESSOR7.3 SOFT CORE PROCESSORS ON AN FPGA7.4 SUMMARYSECTION 3: DESIGNER’S TOOLBOXCHAPTER 8: SERIAL COMMUNICATIONS8.1 INTRODUCTION8.2 MANCHESTER ENCODING AND DECODING8.3 NRZ (NON-RETURN-TO-ZERO) CODING AND DECODING8.4 NRZI (NON-RETURN-TO-ZERO-INVERTED) CODING AND DECODING8.5 RS-2328.6 USB (UNIVERSAL SERIAL BUS)8.7 SUMMARY CHAPTER 9: DIGITAL FILTERS9.1 INTRODUCTION9.2 CONVERTING S DOMAIN TO Z DOMAIN 9.3 IMPLEMENTING Z DOMAIN FUNCTIONS IN VHDL 9.4 BASIC LOW PASS FILTER MODEL9.5 FINITE IMPULSE RESPONSE (FIR) FILTERS 9.6 INFINITE IMPULSE RESPONSE (IIR) FILTERS9.7 SUMMARY CHAPTER 10: SECURE SYSTEMS10.1 INTRODUCTION TO BLOCK CIPHERS10.2 FEISTEL LATTICE STRUCTURES10.3 THE DATA ENCRYPTION STANDARD (DES)10.4 ADVANCED ENCRYPTION STANDARD (AES)CHAPTER 11: MEMORY 11.1 INTRODUCTION11.2 MODELING MEMORY IN VHDL11.3 READ ONLY MEMORY (ROM)11.4 RANDOM ACCESS MEMORY (RAM)11.5 SYNCHRONOUS RAM (SRAM)11.6 SUMMARYCHAPTER 12: PS/2 MOUSE INTERFACE12.1 INTRODUCTION12.2 PS/2 MOUSE BASICS12.3 PS/2 MOUSE COMMANDS12.4 PS/2 MOUSE DATA PACKETS 12.5 PS/2 OPERATION MODES12.6 PS/2 MOUSE WITH WHEEL12.7 BASIC PS/2 MOUSE HANDLER VHDL12.8 MODIFIED PS/2 MOUSE HANDLER VHDL12.9 SUMMARYCHAPTER 13: PS/2 KEYBOARD INTERFACE13.1 INTRODUCTION13.2 PS/2 KEYBOARD BASICS13.3 PS/2 KEYBOARD COMMANDS13.4 PS/2 KEYBOARD DATA PACKETS13.5 PS/2 KEYBOARD OPERATION MODES13.6 BASIC PS/2 KEYBOARD HANDLER VHDL13.7 MODIFIED PS/2 KEYBOARD HANDLER VHDL13.8 SUMMARYCHAPTER 14: A SIMPLE VGA INTERFACE14.1 INTRODUCTION14.2 BASIC PIXEL TIMING14.3 IMAGE HANDLING14.4 VGA INTERFACE VHDL14.5 HORIZONTAL SYNC 14.6 VERTICAL SYNC14.7 HORIZONTAL AND VERTICAL BLANKING PULSES14.8 CALCULATING THE CORRECT PIXEL DATA14.9 SUMMARYSECTION 4: OPTIMIZING DESIGNSCHAPTER 15: ADVANCED TECHNIQUES15.1 INTRODUCTIONCHAPTER 16: SYNTHESIS16.1 INTRODUCTION16.2 VHDL SUPPORTED IN RTL SYNTHESIS 16.3 SOME INTERESTING CASES WHERE SYNTHESIS MAY FAIL16.4 WHAT IS BEING SYNTHESISED?16.5 SUMMARY CHAPTER 17: BEHAVIOURAL MODELING IN VHDL17.1 INTRODUCTION17.2 HOW TO GO FROM RTL TO BEHAVIOURAL VHDL17.3 SUMMARY CHAPTER 18: DESIGN OPTIMIZATION18.1 INTRODUCTION 18.2 TECHNIQUES FOR LOGIC OPTIMIZATION18.3 IMPROVING PERFORMANCE18.4 CRITICAL PATH ANALYSIS18.5 SUMMARYCHAPTER 19: VHDL-AMS19.1 INTRODUCTION19.2 INTRODUCTION TO VHDL-AMS19.3 ANALOGUE PINS – TERMINALS19.4 MIXED DOMAIN MODELING19.5 ANALOGUE VARIABLES – QUANTITIES19.6 SIMULTANEOUS EQUATIONS IN VHDL-AMS19.7 A VHDL-AMS EXAMPLE – A DC VOLTAGE SOURCE19.8 A VHDL-AMS EXAMPLE – RESISTOR19.9 DIFFERENTIAL EQUATIONS IN VHDL-AMS19.10 MIXED SIGNAL MODELING WITH VHDL-AMS19.11 A BASIC SWITCH MODEL19.12 BASIC VHDL-AMS COMPARATOR MODEL19.13 MULTIPLE DOMAIN MODELING19.14 SUMMARY CHAPTER 20: DESIGN OPTIMIZATION EXAMPLE: DES20.1 INTRODUCTION20.2 THE DATA ENCRYPTION STANDARD (DES)20.3 MOODS20.4 INITIAL DESIGN 20.5 INITIAL SYNTHESIS20.6 OPTIMIZING THE DATAPATH 20.7 FINAL OPTIMIZATION20.8 RESULTS20.9 TRIPLE DES20.10 COMPARING THE APPROACHES20.11 SUMMARYSECTION 5: FUNDAMENTAL TECHNIQUESCHAPTER 21: COUNTERS21.1 INTRODUCTION21.2 BASIC BINARY COUNTER21.3 SYNTHESISED SIMPLE BINARY COUNTER21.4 SHIFT REGISTER21.5 THE JOHNSON COUNTER21.6 BCD COUNTER21.7 SUMMARYCHAPTER 22: LATCHES, FLIP-FLOPS AND REGISTERS22.1 INTRODUCTION22.2 LATCHES22.3 FLIP-FLOPS22.4 REGISTERS22.5 SUMMARYCHAPTER 23: SERIAL TO PARALLEL & PARALLEL TO SERIAL CONVERSION23.1 SERIAL TO PARALLEL CONVERSION (SIPO)23.2 PARALLEL TO SERIAL CONVERSION (PISO)23.3 SUMMARYCHAPTER 24: ALU FUNCTIONS24.1 INTRODUCTION24.2 LOGIC FUNCTIONS24.3 1 BIT ADDER24.4 STRUCTURAL N-BIT ADDITION24.5 CONFIGURABLE N-BIT ADDITION24.6 TWOS COMPLEMENT24.7 SUMMARYCHAPTER 25: DECODERS AND MULTIPLEXERS25.1 DECODERS25.2 MULTIPLEXERS25.3 SUMMARYCHAPTER 26: FINITE STATE MACHINES IN VHDL26.1 INTRODUCTION26.2 STATE TRANSITION DIAGRAMS26.3 IMPLEMENTING FINITE STATE MACHINES IN VHDL26.4 SUMMARYCHAPTER 27: FIXED POINT ARITHMETIC IN VHDL27.1 INTRODUCTION27.2 BASIC FIXED POINT TYPES27.3 FIXED POINT FUNCTIONS27.4 TESTING THE FIXED POINT FUNCTION27.5 SUMMARYCHAPTER 28: BINARY MULTIPLICATION28.1 INTRODUCTION28.2 BASIC BINARY MULTIPLICATION28.3 VHDL UNSIGNED MULTIPLIER28.4 SYNTHESIS OF THE MULTIPLICATION FUNCTION28.5 “SIMPLE” MULTIPLICATION28.6 SUMMARYCHAPTER 29: BIBLIOGRAPHY29.1 INTRODUCTION29.2 USEFUL TEXTS FOR VHDL AND FPGA DESIGNERSINDEX

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