Table of ContentsPreface. Conference Organization. Invited Presentation: Real time distributed systems (M.R. Barbacci). BDD-based Design and Analysis Techniques. (Chair: L. Claesen). Verification of the Futurebus+ Cache coherence protocol (E.M. Clarke, O. Grumberg, H. Hiraishi, S. Jha, D.E. Long, K.L. McMillan, L.A. Ness). Exploiting symbolic traversal techniques for efficient Process Algebra Manipulation (P. Camurati, F. Corno, P. Prinetto). Hardware-verification using first order BDDs (K. Schneider, R. Kumar, T. Kropf). HDL-based Design Methods. (Chair: F. Rammig). HW/SW co-design with PRAMs using codes (K. Buchenrieder, A. Sedlmeier, C. Veith). Prevail-DM: a framework-based environment for formal hardware verification (F.R. Wagner). Better verification through symmetry (C.N. Ip, D.L. Dill). Synthesis and Verification. (Chair: M. Barbacci). A rewriting based method for the formal verification of microprocessors (M. Allemand). Reasoning about the VHDL standard logic package signal data type (J.W. Gambles, P.J. Windley). An efficient data-path synthesis based on algorithmic description under the constraints of time and area (X.-J. Xu, M. Ishizuka). Integrating Boolean verification with formal derivation (B. Bose, S.D. Johnson, S. Pullela). Automated high-level verification against clocked algorithmic specifications (F. Corella). The backward walk approach in FSM verification (S. Krischer). Invited Presentation: Automatic verification of sequential circuit designs (E.M. Clarke). Protocol Specification. (Chair: E. Cerny). Toward a basis for protocol specification and process decomposition (K. Rath, S.D. Johnson). Integrating SDL and VHDL for system-level hardware design (W. Glunz, T. Kruse, T. Rössel, D. Monjau). Formal Reasoning about Regular Structures. (Chair: C.D. Kloos). Reasoning about array structures using a dependently typed logic (A. Dent, K. Hanna). VHDL description and formal verification of systolic multipliers (L. Pierre). Transformational rewriting with Ruby (R. Sharp, O. Rasmussen). High Level Synthesis. (Chair: F. Wagner). A representation for the binding of RT-component functionality to HDL behavior (R.P. Ang, N.D. Dutt). Performance specification and measurement (R. Mandayam, R. Vemuri). Automatic synthesis of sequential synchronizations (Z. Zhu, S.D. Johnson). Design Capture (short papers). (Chair: E.M. Clarke). Specifying hardware systems in LOTOS (M. Faci, L. Logrippo). HML: a hardware description language based on standard ML (J. O'Leary, M. Linderman, M. Leeser, M. Aagaard). An efficient object-oriented variation of the statecharts formalism for distributed real-time systems (B. Selic). Linking system design tools and hardware design tools (A.A. Jerraya, K. O'Brien, T. Ben Ismail). Automatic VHDL model generation system (S. Kang, S.A. Szygenda). The modeler's assistant: a CAD tool for behavioral model development (B. Singh, J. Wicks, P. Wright, J.R. Armstrong). Insulin: an instruction set simulation environment (S. Sutarwala, P.G. Paulin, Y. Kumar). Invited Presentation: Specification languages for communication protocols (G. v. Bochmann). Timing Specifications in HDLs. (Chair: J. Brzozowski). Integrating behavior and timing in executable specifications (K. Khordoc, M. Dufresne, E. Cerny, P.A. Babkine, A. Silburt). ESP: an executable specification language for mixed timing control circuits (T.-A. Chu, H.T. Cao, C.K.C. Leung). Textual and Graphical HDLs. (Chair: Robert Hum). UDL/I version two: a new horizon of HDL standards (T. Hoshino). Verilog HDL modeling styles for formal verification (F. Balarin, G. York). A visual hardware description language (E.J. Golin, A.C. Feng). Textual/graphical design concept-level synthesis (W.R. Cyre). VHDL. (Chairs: R. Waxman, P. Bakowski). System-level specification and design using VHDL: a case study (W. Ecker, S. März). A denotational definition of the VHDL simulation kernel (K.C. Davis). Checking DFT rules with a VHDL simulator (W. Glunz, T. Rössel). Parameterized VHDL entities for the simulation of hybrid circuits (M. Ryba, W. Seibold, U.G. Baitinger, U. Thelen). Modeling timing behavior of logic circuits using piecewise linear models (Z. Navabi, A. Hashemi, M. Eghtesad, M. Vai). Analog-VHDL: as an applciation, a real example (D. Rodriguez).