Comprehensive Functional Verification

The Complete Industry Cycle


  • Bruce Wile, IBM Corporation, Poughkeepsie, NY
  • John Goss, IBM Corporation, Research Triangle Park, NC
  • Wolfgang Roesner, IBM Corporation, Austin, TX

One of the biggest challenges in chip and system design is determining whether the hardware works correctly. That is the job of functional verification engineers and they are the audience for this comprehensive text from three top industry professionals.As designs increase in complexity, so has the value of verification engineers within the hardware design team. In fact, the need for skilled verification engineers has grown dramatically--functional verification now consumes between 40 and 70% of a project's labor, and about half its cost. Currently there are very few books on verification for engineers, and none that cover the subject as comprehensively as this text. A key strength of this book is that it describes the entire verification cycle and details each stage. The organization of the book follows the cycle, demonstrating how functional verification engages all aspects of the overall design effort and how individual cycle stages relate to the larger design process. Throughout the text, the authors leverage their 35 plus years experience in functional verification, providing examples and case studies, and focusing on the skills, methods, and tools needed to complete each verification task. Additionally, the major vendors (Mentor Graphics, Cadence Design Systems, Verisity, and Synopsys) have implemented key examples from the text and made these available on line, so that the reader can test out the methods described in the text.
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Sr. undergraduate & graduate students in functional verification courses in EE and Computer Engineering Departments; new and experienced verification engineers


Book information

  • Published: May 2005
  • ISBN: 978-0-12-751803-9


Very good :-)

Table of Contents

Comprehensive Functional Verification: The Complete Industry CyclePart I: Introduction to VerificationChapter 1: Verification in the Chip Design Process1.1 Introduction to Functional Verification1.2 The Verification Challenge1.3 Mission and Goals of Verification1.4 Cost of Verification1.5 Areas of Verification beyond the scope of this book1.6 The Verification Cycle: A Structured Process1.7 Summary1.8 ExercisesChapter 2: Verification Flow2.1 Verification Hierarchy2.2 Strategy of Verification2.3 Summary2.4 ExercisesChapter 3: Fundamentals of Simulation Based Verification 3.1 Basic Verification Environment: A Test Bench3.2 Observation Points: Black-box, White-box and Grey-box verification3.3 Assertion Based Verification – An overview3.4 Test benches and Testing Strategies3.5 Summary3.6 ExercisesChapter 4: The Verification Plan4.1 The Functional Specification4.2 The Evolution of the Verification Plan4.3 Contents of the Verification Plan4.4 Verification example: Calc14.5 Summary4.6 ExercisesPart II: Simulation Based VerificationChapter 5: HDLs and Simulation Engines5.1 Hardware Description Languages5.2 Simulation Engines - Introduction5.3 Event-Driven Simulation5.4 Improving Simulation Throughput5.5 Cycle-Based Simulation 5.6 Waveform Viewers5.7 Summary5.8 ExercisesChapter 6: Creating Environments6.1 Testbench Writing Tools6.2 Verification Coverage 6.3 Summary6.4 ExercisesChapter 7: Strategies for Simulation based Stimulus Generation7.1 Calc2 Overview7.2 Strategies for Stimulus Generation7.3 Summary7.4 ExercisesChapter 8: Strategies for Results Checking in Simulation Based Verification8.1 Types of Result Checking8.2 Debug8.3 Summary8.4 ExercisesChapter 9: Pervasive Function Verification9.1 System Reset and Bring-up9.2 Error and Degraded Mode Handling9.3 Verifying Hardware Debug Assists9.4 Low Power Mode Verification9.5 Summary9.6 ExercisesChapter 10: Re-Use Strategies and System Simulation10.1: Re-Use Strategies10.2: System Simulation10.3: Beyond General Purpose Logic Simulation10.4: Summary10.5: ExercisesPart III: Formal VerificationChapter 11 Introduction to Formal Verification11.1 Foundations11.2 Formal Boolean Equivalence Checking11.3 Functional Formal Verification – Property Checking11.4 Summary11.5 ExercisesChapter 12 Using Formal Verification12.1 Property Specification Using an HDL Library12.2 The Property Specification Language PSL12.3 Property Checking Using Formal Verification12.4 Summary12.5 ExercisesPart IV: Comprehensive VerificationChapter 13: Completing the Verification Cycle13.1 Regression13.2 Problem Tracking13.3 Tape-Out Readiness13.4 Escape Analysis13.5 Summary13.6 ExercisesChapter 14: Advanced Verification Techniques14.1 Save verification cycles – bootstrapping the verification process14.2 High-Level modeling – concepts14.3 Coverage-Directed Generation14.4 Summary14.5 ExercisesPart V: Case StudiesChapter 15: Case Studies15.1 The Line Delete Escape15.2 Branch History Table15.3 Network Processor15.4 SummaryGlossaryReferences