Algorithms and Parallel VLSI Architectures III book cover

Algorithms and Parallel VLSI Architectures III

A comprehensive overview of the current evolution of research in algorithms, architectures and compilation for parallel systems is provided by this publication.

The contributions focus specifically on domains where embedded systems are required, either oriented to application-specific or to programmable realisations. These are crucial in domains such as audio, telecom, instrumentation, speech, robotics, medical and automotive processing, image and video processing, TV, multimedia, radar and sonar.

The book will be of particular interest to the academic community because of the detailed descriptions of research results presented. In addition, many contributions feature the "real-life" applications that are responsible for driving research and the impact of their specific characteristics on the methodologies is assessed.

The publication will also be of considerable value to senior design engineers and CAD managers in the industrial arena, who wish either to anticipate the evolution of commercially available design tools or to utilize the presented concepts in their own R&D programmes.

Hardbound, 424 Pages

Published: March 1995

Imprint: Elsevier

ISBN: 978-0-444-82106-5

Contents

  • Introduction. Algorithms and Parallel VLSI Architectures. Parallel Algorithms. Subspace methods in system identification and source localization (P.A. Regalia). Pipelining the inverse updates RLS array by algorithmic engineering (J. McWhirter, I.K. Proudler). Hierarchical signal flow graph representation of the square-root covariance Kalman filter (D.W. Brown, F.M.F. Gaston). A systolic algorithm for block-regularized RLS identification (J. Schier). Numerical analysis of a normalised RLS filter using a probability description of propagated data (J. Kadlec). Adaptive approximate rotations for computing the symmetric EVD (J. Götze, G.J. Hekstra). Parallel implementation of the double bracket matrix flow for eigenvalue-eigenvector computation and sorting (N. Saxena, J.J. Clark). Parallel block iterative solvers for heterogeneous computing environments (M. Arioli et al.). Efficient VLSI architecture for residue to binary converter (G.C. Cardarilli et al.). Parallel Architectures. A case study in algorithm-architecture codesign: hardware-accelerator for long integer arithmetic (C. Riem, J. König, L. Thiele). An optimisation methodology for mapping a diffusion algorithm for vision into a modular and flexible array architecture (J. Rosseel et al.). A scalable design for dictionary machines (T. Duboux, A. Ferreira, M. Gastaldo). Systolic implementation of Smith and Waterman algorithm on a SIMD coprocessor (D. Archambaud, I. Saraiva Silva, J. Penné). Architecture and programming of parallel video signal processors (K. Vissers et al.). A highly parallel single-chip video signal processor (K. Rönner, J. Kneip, P. Pirsch). A memory efficient, programmable multi-processor architecture for real-time motion estimation type algorithms (E. De Greef, F. Catthoor, H. De Man). Instruction-level parallelism in asynchronous processor architectures (D.K. Arvind, V.E.F. Rebello). High speed wood inspection using a parallel VLSI architecture (M. Hall, A. Aström). CONVEX exemplar systems: scalable parallel processing (J. van Kats). Modelling the 2-D FCT on a multiprocessor system (C.A. Christopoulos, A.N. Skodras, J. Cornelis). Parallel grep (J. Champeau, L. Le Pape, B. Pottier). Parallel Compilation. Compiling for massively parallel architectures: a perspective (P. Feautrier). DIV, FLOOR, CEIL, MOD and STEP functions in nested loop programs and linear bounded lattices (P. Held, B. Kienhuis). Uniformisation techniques for reducible integral recurrence equations (L. Rapanotti, G.M. Megson). HOPP - a higher-order parallel programming model (R. Rangaswami). Design by transformation of synchronous descriptions (G. Durrieu, M. Lemaitre). Heuristics for evaluation of array expressions on state of the art massively parallel machines (V. Bouchitté et al.). On factors limiting the generation of efficient compiler-parallelized programs (M.R. Werth, P. Feautrier). From dependence analysis to communication code generation: the look forwards model (C. Reffay, G.-R. Perrin). Mapping complex image processing algorithms onto heterogeneous multi-processors regarding architecture dependent performance parameters (M. Schwiegershausen, M. Schönfeld, P. Pirsch). Optimal communication for a graph based DSP silicon compiler (H.-K. Kim). Resource-constrained software pipelining for high-level synthesis of DSP systems (F. Sánchez, J. Cortadella). A portable testbed for evaluating different approaches to distributed logic simulation (P. Luksch). A simulator for optical parallel computer architectures (N. Langloh et al.). Authors Index.

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